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Subject: Re: [PATCH 2/2] clk: qcom: Add SC8280XP GPU clock controller
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     Michael Turquette <mturquette@baylibre.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
To:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Konrad Dybcio <konrad.dybcio@somainline.org>,
        Taniya Das <tdas@codeaurora.org>
Date:   Mon, 15 Aug 2022 11:45:53 -0700
User-Agent: alot/0.10
Message-Id: <20220815184555.4210EC43470@smtp.kernel.org>
Precedence: bulk

Quoting Bjorn Andersson (2022-08-10 21:28:55)
> diff --git a/drivers/clk/qcom/gpucc-sc8280xp.c b/drivers/clk/qcom/gpucc-s=
c8280xp.c
> new file mode 100644
> index 000000000000..555fd4ff58ab
> --- /dev/null
> +++ b/drivers/clk/qcom/gpucc-sc8280xp.c
> @@ -0,0 +1,460 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>

include kernel.h for ARRAY_SIZE please.

> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap-divider.h"
> +#include "common.h"
> +#include "reset.h"
> +#include "gdsc.h"
> +
> +/* Need to match the order of clocks in DT binding */
> +enum {
> +       DT_BI_TCXO,
> +       DT_GCC_GPU_GPLL0_CLK_SRC,
> +       DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
> +};
> +
> +enum {
> +       P_BI_TCXO,
> +       P_GCC_GPU_GPLL0_CLK_SRC,
> +       P_GCC_GPU_GPLL0_DIV_CLK_SRC,
> +       P_GPU_CC_PLL0_OUT_MAIN,
> +       P_GPU_CC_PLL1_OUT_MAIN,
> +};
> +
> +static const struct clk_parent_data parent_data_tcxo =3D { .index =3D DT=
_BI_TCXO };
> +
> +static const struct pll_vco lucid_5lpe_vco[] =3D {
> +       { 249600000, 1800000000, 0 },
> +};
> +
> +static struct alpha_pll_config gpu_cc_pll0_config =3D {
> +       .l =3D 0x1c,
> +       .alpha =3D 0xa555,
> +       .config_ctl_val =3D 0x20485699,
> +       .config_ctl_hi_val =3D 0x00002261,
> +       .config_ctl_hi1_val =3D 0x2a9a699c,
> +       .test_ctl_val =3D 0x00000000,
> +       .test_ctl_hi_val =3D 0x00000000,
> +       .test_ctl_hi1_val =3D 0x01800000,
> +       .user_ctl_val =3D 0x00000000,
> +       .user_ctl_hi_val =3D 0x00000805,
> +       .user_ctl_hi1_val =3D 0x00000000,
> +};
> +
> +static struct clk_alpha_pll gpu_cc_pll0 =3D {
> +       .offset =3D 0x0,
> +       .vco_table =3D lucid_5lpe_vco,
> +       .num_vco =3D ARRAY_SIZE(lucid_5lpe_vco),
> +       .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
> +       .clkr =3D {
> +               .hw.init =3D &(struct clk_init_data){

const?

> +                       .name =3D "gpu_cc_pll0",
> +                       .parent_data =3D &parent_data_tcxo,
> +                       .num_parents =3D 1,
> +                       .ops =3D &clk_alpha_pll_lucid_5lpe_ops,
> +               },
> +       },
> +};