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From:   <Conor.Dooley@microchip.com>
To:     <prabhakar.csengg@gmail.com>, <Conor.Dooley@microchip.com>
CC:     <prabhakar.mahadev-lad.rj@bp.renesas.com>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <paul.walmsley@sifive.com>,
        <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
        <geert+renesas@glider.be>, <anup@brainfault.org>,
        <linux-renesas-soc@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
        <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five
 SoC
Thread-Topic: [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas
 RZ/Five SoC
Thread-Index: AQHYsLoNIrzcJ1b/ykeOQ3jLymgw4q2wTvmAgAAOjYCAAAEtAA==
Date:   Mon, 15 Aug 2022 19:49:06 +0000
Message-ID: <c7889bcb-c765-a30c-6d93-c6c1ac0152e3@microchip.com>
References: <20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20220815151451.23293-9-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <ca555430-055c-debb-fdb4-fa7f78129780@microchip.com>
 <CA+V-a8s=RoZmMvDqnBpYZTR2uotv6srumeoRn2=828zhAbOQZA@mail.gmail.com>
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