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[2620:137:e000::1:20]) by mx.google.com with ESMTP id nd38-20020a17090762a600b0073159d67b74si9221975ejc.46.2022.08.15.17.40.28; Mon, 15 Aug 2022 17:40:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linuxfoundation.org header.s=korg header.b=EUyJIKaT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linuxfoundation.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229843AbiHOW7t (ORCPT + 99 others); Mon, 15 Aug 2022 18:59:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352396AbiHOW5r (ORCPT ); Mon, 15 Aug 2022 18:57:47 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D012696EF; Mon, 15 Aug 2022 12:56:23 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A37106068D; Mon, 15 Aug 2022 19:56:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A4B5FC433C1; Mon, 15 Aug 2022 19:56:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1660593382; bh=XEDSV78Q/YnvAycgd6lJT1iDcVXabsyL2dsy4Yff5+w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EUyJIKaTfvrIFCuB2ke7iEAEHebnUumMhtb/k+1GxMF0kPDU+rBCIbWcrnRNkRh8O BY/h1bYz1zMPuV1DUBhvTBK+PI29gBKmFRWp5475rokBZceRSVM5k8Ri5XGee2gy3i +QgtByc0hsnFihoK2pKI7Jmqpulm0KDlWY3/xZGM= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Johan Hovold , Dmitry Baryshkov , Bjorn Andersson , Sasha Levin Subject: [PATCH 5.19 0259/1157] arm64: dts: qcom: sc7280: drop PCIe PHY clock index Date: Mon, 15 Aug 2022 19:53:35 +0200 Message-Id: <20220815180449.932783291@linuxfoundation.org> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220815180439.416659447@linuxfoundation.org> References: <20220815180439.416659447@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Johan Hovold [ Upstream commit 531c738fb36069d60aff267a0b25533a35d59fd0 ] The QMP PCIe PHY provides a single clock so drop the redundant clock index. Signed-off-by: Johan Hovold Fixes: bd7d507935ca ("arm64: dts: qcom: sc7280: Add pcie clock support") Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes") Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220705114032.22787-2-johan+linaro@kernel.org Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index d22405658f13..116b3e0abe93 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -818,7 +818,7 @@ gcc: clock-controller@100000 { reg = <0 0x00100000 0 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <&pcie1_lane 0>, + <0>, <&pcie1_lane>, <0>, <0>, <0>, <0>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk", @@ -2110,7 +2110,7 @@ pcie1_lane: phy@1c0e200 { clock-names = "pipe0"; #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clock-output-names = "pcie_1_pipe_clk"; }; }; -- 2.35.1