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From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Mon, 15 Aug 2022 21:16:13 +0100
Message-ID: <CA+V-a8uNRr+WPX=YC+UMT4ch4S5XwsatHCzUoSt+hTk4C=cheA@mail.gmail.com>
Subject: Re: [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas
 RZ/Five SMARC EVK
To:     Conor.Dooley@microchip.com
Cc:     "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Anup Patel <anup@brainfault.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        LKML <linux-kernel@vger.kernel.org>,
        Biju Das <biju.das.jz@bp.renesas.com>
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Hi Conor,

On Mon, Aug 15, 2022 at 8:00 PM <Conor.Dooley@microchip.com> wrote:
>
> On 15/08/2022 16:14, Lad Prabhakar wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Enable the minimal blocks required for booting the Renesas RZ/Five
> > SMARC EVK with initramfs.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > * New patch
> > ---
> >  arch/riscv/boot/dts/Makefile                  |  1 +
> >  arch/riscv/boot/dts/renesas/Makefile          |  2 ++
> >  .../boot/dts/renesas/r9a07g043f01-smarc.dts   | 16 ++++++++++
> >  .../boot/dts/renesas/rzfive-smarc-som.dtsi    | 22 +++++++++++++
> >  arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++
> >  5 files changed, 73 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/renesas/Makefile
> >  create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> >  create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
>
> Just to sort out some of my own confusion here - is the smarc EVK
> shared between your arm boards and the riscv ones? Or just the
> peripherals etc on the soc?
>
RZ/Five SoC is pin compatible with RZ/G2UL Type 1 SoC (ARM64). RZ/G2UL
SMARC EVK carrier board can be swapped with RZ/Five or RZ/G2UL SMARC
SoM and still be used.

> If it is the forver, does the approach suggested here for the
> allwinner stuff make sense to also use for risc-v stuff with
> shared parts of devicetrees?
> https://lore.kernel.org/linux-riscv/3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com/
>
it does make sense. But I wonder where we would place the common
shared dtsi that can be used by two arch's.

> Would at least be interesting in hearing more opinions from the dt
> people, Geert & Palmer. We have some SOM based stuff too with carriers
> so I am interested in seeing how the cross platform part of that works
> out.
>
Yep, that would be interesting.

Cheers,
Prabhakar