Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Tue, 16 Aug 2022 09:42:16 +0200
From:   Daniel =?iso-8859-1?Q?Gl=F6ckner?= <dg@emlix.com>
To:     Xu Yilun <yilun.xu@intel.com>
Cc:     Ivan Bornyakov <i.bornyakov@metrotek.ru>, mdf@kernel.org,
        hao.wu@intel.com, trix@redhat.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, linux-fpga@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        system@metrotek.ru
Subject: Re: [PATCH v6 1/2] fpga: ecp5-spi: add Lattice ECP5 FPGA manager
Message-ID: <20220816074216.GA31706@homes.emlix.com>
References: <20220815132157.8083-1-i.bornyakov@metrotek.ru>
 <20220815132157.8083-2-i.bornyakov@metrotek.ru>
 <Yvr6SY5WGXlYiLig@yilunxu-OptiPlex-7050>
 <20220816045841.irhr5vigemdqknaw@x260>
 <Yvs0jieXsyzhn8q9@yilunxu-OptiPlex-7050>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <Yvs0jieXsyzhn8q9@yilunxu-OptiPlex-7050>
User-Agent: Mutt/1.10.1 (2018-07-13)
Precedence: bulk

On Tue, Aug 16, 2022 at 02:09:18PM +0800, Xu Yilun wrote:
> We don't have to make everything fine, but start with machxo2 and ecp5
> first. If the change affects machxo2, other people may help.

Programming MachXO* chips uses different sequences of commands. With ECP5
you put the chip into configuration mode and then upload the bitstream
into RAM cells. With MachXO chips you write the bitstream to non-volatile
storage and then tell the chip to go into configuration mode where it
automatically loads the bitstream from non-volatile storage. There is no
way to directly write the RAM cells.

Best regards,

  Daniel