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[2001:14bb:ae:539c:1b1c:14b7:109b:ed76]) by smtp.gmail.com with ESMTPSA id h25-20020ac24d39000000b0048b2be5320csm1576801lfk.118.2022.08.16.23.05.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Aug 2022 23:05:52 -0700 (PDT) Message-ID: <6c283634-70b3-200f-a346-28eb4c428d39@linaro.org> Date: Wed, 17 Aug 2022 09:05:51 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: qcom: Add sc8280xp lpass lpi pinctrl bindings Content-Language: en-US To: Srinivas Kandagatla , agross@kernel.org, bjorn.andersson@linaro.org, linus.walleij@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20220816180538.9039-1-srinivas.kandagatla@linaro.org> <20220816180538.9039-2-srinivas.kandagatla@linaro.org> From: Krzysztof Kozlowski In-Reply-To: <20220816180538.9039-2-srinivas.kandagatla@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16/08/2022 21:05, Srinivas Kandagatla wrote: > Add device tree binding Documentation details for Qualcomm SC8280XP > LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctrl driver. > > Signed-off-by: Srinivas Kandagatla Thank you for your patch. There is something to discuss/improve. > + gpio-ranges: > + maxItems: 1 > + > +#PIN CONFIGURATION NODES > +patternProperties: > + '-pins$': > + type: object > + description: > + Pinctrl node's client devices use subnodes for desired pin configuration. > + Client device subnodes use below standard properties. > + $ref: "/schemas/pinctrl/pincfg-node.yaml" Drop the quotes. > + > + properties: > + pins: > + description: > + List of gpio pins affected by the properties specified in this > + subnode. > + items: > + pattern: "^gpio([0-1]|[0-8]])$" error in pattern - double ]. If you have 19 GPIOs, this should be probably: ^gpio([0-9]|1[0-8])$ > + > + function: > + enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data, > + dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk, > + dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data, > + qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws, > + i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk, > + wsa2_swr_data, i2s2_data, i2s3_clk, i2s3_ws, i2s3_data, > + ext_mclk1_c, ext_mclk1_b, ext_mclk1_a ] > + Skip blank line (confuses with a new property). > + description: > + Specify the alternative function to be configured for the specified > + pins. > + > + drive-strength: > + enum: [2, 4, 6, 8, 10, 12, 14, 16] > + default: 2 > + description: > + Selects the drive strength for the specified pins, in mA. > + > + slew-rate: > + enum: [0, 1, 2, 3] > + default: 0 > + description: | > + 0: No adjustments > + 1: Higher Slew rate (faster edges) > + 2: Lower Slew rate (slower edges) > + 3: Reserved (No adjustments) > + > + bias-pull-down: true > + > + bias-pull-up: true > + > + bias-disable: true > + > + output-high: true > + > + output-low: true > + > + required: > + - pins > + - function > + > + additionalProperties: false > + > +allOf: > + - $ref: "pinctrl.yaml#" Drop the quotes. > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - gpio-controller > + - '#gpio-cells' > + - gpio-ranges > + > +additionalProperties: false > + > +examples: > + - | > + #include > + lpi_tlmm: pinctrl@33c0000 { Drop the label, not used anywhere here. > + compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; > + reg = <0x33c0000 0x20000>, > + <0x3550000 0x10000>; > + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; > + clock-names = "core", "audio"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&lpi_tlmm 0 0 18>; > + }; Best regards, Krzysztof