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[77.158.188.58]) by smtp.gmail.com with ESMTPSA id u15-20020a05600c19cf00b003a54d610e5fsm1391992wmq.26.2022.08.17.01.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 01:08:50 -0700 (PDT) From: bchihi@baylibre.com To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v9,5/7] arm64: dts: mt8195: Add efuse node to mt8195 Date: Wed, 17 Aug 2022 10:07:55 +0200 Message-Id: <20220817080757.352021-6-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220817080757.352021-1-bchihi@baylibre.com> References: <20220817080757.352021-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alexandre Bailon Add efuse node. This will be required by the thermal driver to get the calibration data. Signed-off-by: Alexandre Bailon Co-developed-by: Balsam CHIHI Signed-off-by: Balsam CHIHI --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 066c14989708..95967a0196d8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -733,6 +733,18 @@ u2_intr_p3: usb2-intr-p3@189,2 { reg = <0x189 0x2>; bits = <7 5>; }; + + lvts_efuse_data1: lvts1-calib@1bc { + reg = <0x1bc 0x14>; + }; + + lvts_efuse_data2: lvts2-calib@1d0 { + reg = <0x1d0 0x38>; + }; + + svs_calibration: calib@580 { + reg = <0x580 0x64>; + }; }; u3phy2: t-phy@11c40000 { -- 2.34.1