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From:   "Manne, Nava kishore" <nava.kishore.manne@amd.com>
To:     Xu Yilun <yilun.xu@intel.com>,
        Nava kishore Manne <nava.manne@xilinx.com>
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Subject: RE: [PATCH v2 3/3] fpga: zynqmp-fpga: Adds status interface
Thread-Topic: [PATCH v2 3/3] fpga: zynqmp-fpga: Adds status interface
Thread-Index: AQHYhVFwpTOzhNAppEePIKhgjmp+4K1kisgAgE63IDA=
Date:   Wed, 17 Aug 2022 10:45:14 +0000
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References: <20220621092833.1057408-1-nava.manne@xilinx.com>
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 <20220628084024.GB2442728@yilunxu-OptiPlex-7050>
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Hi Yilun,

	Please find my response inline.

> -----Original Message-----
> From: Xu Yilun <yilun.xu@intel.com>
> Sent: Tuesday, June 28, 2022 2:10 PM
> To: Nava kishore Manne <nava.manne@xilinx.com>
> Cc: michal.simek@xilinx.com; hao.wu@intel.com; trix@redhat.com;
> mdf@kernel.org; gregkh@linuxfoundation.org; ronak.jain@xilinx.com;
> rajan.vaja@xilinx.com; abhyuday.godhasara@xilinx.com;
> piyush.mehta@xilinx.com; harsha.harsha@xilinx.com;
> lakshmi.sai.krishna.potthuri@xilinx.com; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> fpga@vger.kernel.org; git@xilinx.com
> Subject: Re: [PATCH v2 3/3] fpga: zynqmp-fpga: Adds status interface
>=20
> CAUTION: This message has originated from an External Source. Please use
> proper judgment and caution when opening attachments, clicking links, or
> responding to this email.
>=20
>=20
> On Tue, Jun 21, 2022 at 02:58:33PM +0530, Nava kishore Manne wrote:
> > Adds status interface for zynqmp-fpga, It's a read only interface
> > which allows the user to get the PL status.
> >
> > Usage:
> > To read the PL configuration status
> >         cat /sys/class/fpga_manager/<fpga>/status
> >
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > ---
> > Changes for v2:
> >               - Updated status messages handling logic as suggested by =
Xu Yilun.
> >
> >  drivers/fpga/zynqmp-fpga.c | 53
> > ++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 53 insertions(+)
> >
> > diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
> > index c60f20949c47..e194bba91d3f 100644
> > --- a/drivers/fpga/zynqmp-fpga.c
> > +++ b/drivers/fpga/zynqmp-fpga.c
> > @@ -14,6 +14,19 @@
> >
> >  /* Constant Definitions */
> >  #define IXR_FPGA_DONE_MASK   BIT(3)
> > +#define READ_DMA_SIZE                256U
> > +
> > +/* Error Register */
> > +#define IXR_FPGA_ERR_CRC_ERR         BIT(0)
> > +#define IXR_FPGA_ERR_SECURITY_ERR    BIT(16)
> > +
> > +/* Signal Status Register. For details refer ug570 */
> > +#define IXR_FPGA_END_OF_STARTUP              BIT(4)
> > +#define IXR_FPGA_GST_CFG_B           BIT(5)
> > +#define IXR_FPGA_INIT_B_INTERNAL     BIT(11)
> > +#define IXR_FPGA_DONE_INTERNAL_SIGNAL        BIT(13)
> > +
> > +#define IXR_FPGA_CONFIG_STAT_OFFSET  7U
> >
> >  /**
> >   * struct zynqmp_fpga_priv - Private data structure @@ -77,8 +90,48
> > @@ static enum fpga_mgr_states zynqmp_fpga_ops_state(struct
> fpga_manager *mgr)
> >       return FPGA_MGR_STATE_UNKNOWN;
> >  }
> >
> > +static ssize_t zynqmp_fpga_ops_status(struct fpga_manager *mgr, char
> > +*buf) {
> > +     unsigned int *kbuf, reg_val;
> > +     dma_addr_t dma_addr;
> > +     ssize_t len =3D 0;
> > +     int ret;
> > +
> > +     kbuf =3D dma_alloc_coherent(mgr->dev.parent, READ_DMA_SIZE,
> > +                               &dma_addr, GFP_KERNEL);
> > +     if (!kbuf)
> > +             return -ENOMEM;
> > +
> > +     ret =3D zynqmp_pm_fpga_read(IXR_FPGA_CONFIG_STAT_OFFSET,
> dma_addr,
> > +                               PM_FPGA_READ_CONFIG_REG, &reg_val);
> > +     if (ret) {
> > +             len +=3D sprintf(buf + len, "firmware error\n");
> > +             goto free_dmabuf;
> > +     }
> > +
> > +     if (reg_val & IXR_FPGA_ERR_CRC_ERR)
> > +             len +=3D sprintf(buf + len, "reconfig CRC error\n");
> > +     if (reg_val & IXR_FPGA_ERR_SECURITY_ERR)
> > +             len +=3D sprintf(buf + len, "reconfig security error\n");
> > +     if (!(reg_val & IXR_FPGA_INIT_B_INTERNAL))
> > +             len +=3D sprintf(buf + len, "Device Initialization error\=
n");
> > +     if (!(reg_val & IXR_FPGA_DONE_INTERNAL_SIGNAL))
> > +             len +=3D sprintf(buf + len, "Device internal signal error=
\n");
> > +     if (!(reg_val & IXR_FPGA_GST_CFG_B))
> > +             len +=3D sprintf(buf + len,
> > +                            "All I/Os are placed in High-Z state\n");
> > +     if (!(reg_val & IXR_FPGA_END_OF_STARTUP))
> > +             len +=3D sprintf(buf + len, "Device sequence error\n");
>=20
> Expressing multiple lines of data is discouraged, one value or an array o=
f
> values is OK. For more details, see Documentation/filesystems/sysfs.rst
>=20
Will fix.

Regards,
Navakishore.