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From:   <Conor.Dooley@microchip.com>
To:     <heinrich.schuchardt@canonical.com>, <robh+dt@kernel.org>
CC:     <paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
        <aou@eecs.berkeley.edu>, <geert@linux-m68k.org>,
        <emil.renner.berthing@canonical.com>, <devicetree@vger.kernel.org>,
        <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
        <stable@vger.kernel.org>, <atishp@rivosinc.com>,
        <krzysztof.kozlowski+dt@linaro.org>, <Daire.McNamara@microchip.com>
Subject: Re: [PATCH 1/1] riscv: dts: microchip: correct L2 cache interrupts
Thread-Topic: [PATCH 1/1] riscv: dts: microchip: correct L2 cache interrupts
Thread-Index: AQHYsjzjuV6JQqnbNU6bXELDL6GyqK2zYxOA
Date:   Wed, 17 Aug 2022 18:04:21 +0000
Message-ID: <32a72954-c692-6c5d-b07b-266d426c3cb4@microchip.com>
References: <20220817132521.3159388-1-heinrich.schuchardt@canonical.com>
In-Reply-To: <20220817132521.3159388-1-heinrich.schuchardt@canonical.com>
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