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Message-ID: <1d8ff716-598d-617a-34d7-62a433632f78@gmail.com>
Date:   Thu, 18 Aug 2022 04:31:42 +0900
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Subject: Re: [PATCH v2 1/9] dt-bindings: clock: Add bindings for Exynos850
 CMU_AUD
Content-Language: en-US
To:     Sam Protsenko <semen.protsenko@linaro.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Sylwester Nawrocki <s.nawrocki@samsung.com>,
        Chanwoo Choi <cw00.choi@samsung.com>
Cc:     Alim Akhtar <alim.akhtar@samsung.com>,
        Chanho Park <chanho61.park@samsung.com>,
        David Virag <virag.david003@gmail.com>,
        Marek Szyprowski <m.szyprowski@samsung.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Sumit Semwal <sumit.semwal@linaro.org>,
        Tomasz Figa <tomasz.figa@gmail.com>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-samsung-soc@vger.kernel.org
References: <20220809113323.29965-1-semen.protsenko@linaro.org>
 <20220809113323.29965-2-semen.protsenko@linaro.org>
From:   Chanwoo Choi <cwchoi00@gmail.com>
In-Reply-To: <20220809113323.29965-2-semen.protsenko@linaro.org>
Content-Type: text/plain; charset=UTF-8
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Precedence: bulk

On 22. 8. 9. 20:33, Sam Protsenko wrote:
> CMU_AUD generates Cortex-A32 clock, bus clock and audio clocks for
> BLK_AUD. Add clock indices and binding documentation for CMU_AUD.
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> ---
> Changes in v2:
>   - (none)
> 
>  .../clock/samsung,exynos850-clock.yaml        | 19 ++++++
>  include/dt-bindings/clock/exynos850.h         | 68 ++++++++++++++++++-
>  2 files changed, 86 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> index aa11815ad3a3..53511f056251 100644
> --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> @@ -33,6 +33,7 @@ properties:
>      enum:
>        - samsung,exynos850-cmu-top
>        - samsung,exynos850-cmu-apm
> +      - samsung,exynos850-cmu-aud
>        - samsung,exynos850-cmu-cmgp
>        - samsung,exynos850-cmu-core
>        - samsung,exynos850-cmu-dpu
> @@ -88,6 +89,24 @@ allOf:
>              - const: oscclk
>              - const: dout_clkcmu_apm_bus
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: samsung,exynos850-cmu-aud
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (26 MHz)
> +            - description: AUD clock (from CMU_TOP)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +            - const: dout_aud
> +
>    - if:
>        properties:
>          compatible:
> diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
> index 0b6a3c6a7c90..3dc55d4e5b9e 100644
> --- a/include/dt-bindings/clock/exynos850.h
> +++ b/include/dt-bindings/clock/exynos850.h
> @@ -58,7 +58,10 @@
>  #define CLK_MOUT_CLKCMU_APM_BUS		46
>  #define CLK_DOUT_CLKCMU_APM_BUS		47
>  #define CLK_GOUT_CLKCMU_APM_BUS		48
> -#define TOP_NR_CLK			49
> +#define CLK_MOUT_AUD			49
> +#define CLK_GOUT_AUD			50
> +#define CLK_DOUT_AUD			51
> +#define TOP_NR_CLK			52
>  
>  /* CMU_APM */
>  #define CLK_RCO_I3C_PMIC		1
> @@ -87,6 +90,69 @@
>  #define CLK_GOUT_SYSREG_APM_PCLK	24
>  #define APM_NR_CLK			25
>  
> +/* CMU_AUD */
> +#define CLK_DOUT_AUD_AUDIF		1
> +#define CLK_DOUT_AUD_BUSD		2
> +#define CLK_DOUT_AUD_BUSP		3
> +#define CLK_DOUT_AUD_CNT		4
> +#define CLK_DOUT_AUD_CPU		5
> +#define CLK_DOUT_AUD_CPU_ACLK		6
> +#define CLK_DOUT_AUD_CPU_PCLKDBG	7
> +#define CLK_DOUT_AUD_FM			8
> +#define CLK_DOUT_AUD_FM_SPDY		9
> +#define CLK_DOUT_AUD_MCLK		10
> +#define CLK_DOUT_AUD_UAIF0		11
> +#define CLK_DOUT_AUD_UAIF1		12
> +#define CLK_DOUT_AUD_UAIF2		13
> +#define CLK_DOUT_AUD_UAIF3		14
> +#define CLK_DOUT_AUD_UAIF4		15
> +#define CLK_DOUT_AUD_UAIF5		16
> +#define CLK_DOUT_AUD_UAIF6		17
> +#define CLK_FOUT_AUD_PLL		18
> +#define CLK_GOUT_AUD_ABOX_ACLK		19
> +#define CLK_GOUT_AUD_ASB_CCLK		20
> +#define CLK_GOUT_AUD_CA32_CCLK		21
> +#define CLK_GOUT_AUD_CNT_BCLK		22
> +#define CLK_GOUT_AUD_CODEC_MCLK		23
> +#define CLK_GOUT_AUD_DAP_CCLK		24
> +#define CLK_GOUT_AUD_GPIO_PCLK		25
> +#define CLK_GOUT_AUD_PPMU_ACLK		26
> +#define CLK_GOUT_AUD_PPMU_PCLK		27
> +#define CLK_GOUT_AUD_SPDY_BCLK		28
> +#define CLK_GOUT_AUD_SYSMMU_CLK		29
> +#define CLK_GOUT_AUD_SYSREG_PCLK	30
> +#define CLK_GOUT_AUD_TZPC_PCLK		31
> +#define CLK_GOUT_AUD_UAIF0_BCLK		32
> +#define CLK_GOUT_AUD_UAIF1_BCLK		33
> +#define CLK_GOUT_AUD_UAIF2_BCLK		34
> +#define CLK_GOUT_AUD_UAIF3_BCLK		35
> +#define CLK_GOUT_AUD_UAIF4_BCLK		36
> +#define CLK_GOUT_AUD_UAIF5_BCLK		37
> +#define CLK_GOUT_AUD_UAIF6_BCLK		38
> +#define CLK_GOUT_AUD_WDT_PCLK		39
> +#define CLK_MOUT_AUD_CPU		40
> +#define CLK_MOUT_AUD_CPU_HCH		41
> +#define CLK_MOUT_AUD_CPU_USER		42
> +#define CLK_MOUT_AUD_FM			43
> +#define CLK_MOUT_AUD_PLL		44
> +#define CLK_MOUT_AUD_TICK_USB_USER	45
> +#define CLK_MOUT_AUD_UAIF0		46
> +#define CLK_MOUT_AUD_UAIF1		47
> +#define CLK_MOUT_AUD_UAIF2		48
> +#define CLK_MOUT_AUD_UAIF3		49
> +#define CLK_MOUT_AUD_UAIF4		50
> +#define CLK_MOUT_AUD_UAIF5		51
> +#define CLK_MOUT_AUD_UAIF6		52
> +#define IOCLK_AUDIOCDCLK0		53
> +#define IOCLK_AUDIOCDCLK1		54
> +#define IOCLK_AUDIOCDCLK2		55
> +#define IOCLK_AUDIOCDCLK3		56
> +#define IOCLK_AUDIOCDCLK4		57
> +#define IOCLK_AUDIOCDCLK5		58
> +#define IOCLK_AUDIOCDCLK6		59
> +#define TICK_USB			60
> +#define AUD_NR_CLK			61
> +
>  /* CMU_CMGP */
>  #define CLK_RCO_CMGP			1
>  #define CLK_MOUT_CMGP_ADC		2

Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Samsung Electronics
Chanwoo Choi