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Date:   Wed, 17 Aug 2022 19:52:16 +0000
From:   William McVicker <willmcvicker@google.com>
To:     Matthias Kaehlcke <mka@chromium.org>
Cc:     Bjorn Helgaas <bhelgaas@google.com>, kernel-team@android.com,
        Sajid Dalvi <sdalvi@google.com>, linux-pci@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] PCI/PM: Switch D3Hot delay to also use usleep_range
Message-ID: <Yv1G8A5Ut9trpK/L@google.com>
References: <20220817185202.1689955-1-willmcvicker@google.com>
 <Yv1BSfkd6WUh2SFp@google.com>
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On 08/17/2022, Matthias Kaehlcke wrote:
> Hi Will,
> 
> On Wed, Aug 17, 2022 at 06:52:02PM +0000, Will McVicker wrote:
> > From: Sajid Dalvi <sdalvi@google.com>
> > 
> > Since the PCI spec requires a 10ms D3Hot delay (defined by
> > PCI_PM_D3HOT_WAIT) and a few of the PCI quirks update the D3Hot delay up
> > to 120ms, let's add support for both usleep_range and msleep based on
> > the delay time to improve the delay accuracy.
> > 
> > This patch is based off of a commit from Sajid Dalvi <sdalvi@google.com>
> > in the Pixel 6 kernel tree [1]. Testing on a Pixel 6, found that the
> > 10ms delay for the Exynos PCIe device was on average delaying for 19ms
> > when the spec requires 10ms. Switching from msleep to uslseep_range
> > therefore decreases the resume time on a Pixel 6 on average by 9ms.
> > 
> > [1] https://android.googlesource.com/kernel/gs/+/18a8cad68d8e6d50f339a716a18295e6d987cee3
> > 
> > Signed-off-by: Sajid Dalvi <sdalvi@google.com>
> > Signed-off-by: Will McVicker <willmcvicker@google.com>
> > ---
> >  drivers/pci/pci.c | 20 +++++++++++++++-----
> >  1 file changed, 15 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> > index 95bc329e74c0..97a042ca9032 100644
> > --- a/drivers/pci/pci.c
> > +++ b/drivers/pci/pci.c
> > @@ -63,16 +63,26 @@ struct pci_pme_device {
> >  };
> >  
> >  #define PME_TIMEOUT 1000 /* How long between PME checks */
> > +#define MAX(a, b) ((a) >= (b) ? (a) : (b))
> 
> no need to define this macro, you can use max() from
> include/linux/minmax.h instead.
> 
> >  
> >  static void pci_dev_d3_sleep(struct pci_dev *dev)
> >  {
> > -	unsigned int delay = dev->d3hot_delay;
> > +	unsigned int delay_ms = dev->d3hot_delay;
> >  
> > -	if (delay < pci_pm_d3hot_delay)
> > -		delay = pci_pm_d3hot_delay;
> > +	if (delay_ms < pci_pm_d3hot_delay)
> > +		delay_ms = pci_pm_d3hot_delay;
> 
> nit: since you are already touching this code you could change it to:
> 
> 	unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
> 
> >  
> > -	if (delay)
> > -		msleep(delay);
> > +	if (delay_ms) {
> > +		if (delay_ms <= 20) {
> > +			/* Use a 20-25% upper bound with 1ms minimum */
> > +			unsigned int upper = MAX((delay_ms >> 3) << 1, 1);
> 
> Not sure this optimization of using bit shifts instead of the clearer do_div()
> is really needed here. pci_dev_d3_sleep() is not a super hot code path IIUC.
> 
> > +
> > +			usleep_range(delay_ms * USEC_PER_MSEC,
> > +				     (delay_ms + upper) * USEC_PER_MSEC);
> > +		} else {
> > +			msleep(delay_ms);
> > +		}
> > +	}
> >  }
> >  
> >  bool pci_reset_supported(struct pci_dev *dev)
> > 
> > base-commit: 274a2eebf80c60246f9edd6ef8e9a095ad121264
> > -- 
> > 2.37.1.595.g718a3a8f04-goog
> > 

Thanks for the suggestions! I'll update those in the next patchset.

--Will