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[209.85.128.53]) by smtp.gmail.com with ESMTPSA id w22-20020a17090633d600b0072b33e91f96sm7308808eja.190.2022.08.17.15.54.47 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Aug 2022 15:54:47 -0700 (PDT) Received: by mail-wm1-f53.google.com with SMTP id c187-20020a1c35c4000000b003a30d88fe8eso1742250wma.2 for ; Wed, 17 Aug 2022 15:54:47 -0700 (PDT) X-Received: by 2002:a05:600c:42c3:b0:3a6:431:91bf with SMTP id j3-20020a05600c42c300b003a6043191bfmr3178011wme.188.1660776886931; Wed, 17 Aug 2022 15:54:46 -0700 (PDT) MIME-Version: 1.0 References: <20220815093905.134164-1-hsinyi@chromium.org> In-Reply-To: <20220815093905.134164-1-hsinyi@chromium.org> From: Doug Anderson Date: Wed, 17 Aug 2022 15:54:35 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] drm/bridge: ps8640: Add double reset T4 and T5 to power-on sequence To: Hsin-Yi Wang Cc: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , dri-devel , LKML , rock.chiu@paradetech.corp-partner.google.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Mon, Aug 15, 2022 at 2:39 AM Hsin-Yi Wang wrote: > > The double reset power-on sequence is a workaround for the hardware > flaw in some chip that SPI Clock output glitch and cause internal MPU > unable to read firmware correctly. The sequence is suggested in ps8640 > application note. > > Signed-off-by: Hsin-Yi Wang > --- > drivers/gpu/drm/bridge/parade-ps8640.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c > index 49107a6cdac18..d7483c13c569b 100644 > --- a/drivers/gpu/drm/bridge/parade-ps8640.c > +++ b/drivers/gpu/drm/bridge/parade-ps8640.c > @@ -375,6 +375,11 @@ static int __maybe_unused ps8640_resume(struct device *dev) > gpiod_set_value(ps_bridge->gpio_reset, 1); > usleep_range(2000, 2500); > gpiod_set_value(ps_bridge->gpio_reset, 0); > + /* Double reset for T4 and T5 */ > + msleep(50); > + gpiod_set_value(ps_bridge->gpio_reset, 1); > + msleep(50); > + gpiod_set_value(ps_bridge->gpio_reset, 0); We really need another 100 ms here? ps8640 is already quite slow at powering itself up and that has a real user impact. Why was it only 2.5 ms for the first reset and 50 ms for the second? -Doug