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From:   Hsin-Yi Wang <hsinyi@chromium.org>
Date:   Thu, 18 Aug 2022 11:22:23 +0800
Message-ID: <CAJMQK-jEgRq68JXSWtS4y5_39vJ1pWCT2-Atg31__veRtnuREA@mail.gmail.com>
Subject: Re: [PATCH] drm/bridge: ps8640: Add double reset T4 and T5 to
 power-on sequence
To:     Rock Chiu <rock.chiu@paradetech.corp-partner.google.com>
Cc:     Doug Anderson <dianders@chromium.org>,
        Andrzej Hajda <andrzej.hajda@intel.com>,
        Neil Armstrong <narmstrong@baylibre.com>,
        Robert Foss <robert.foss@linaro.org>,
        Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
        Jonas Karlman <jonas@kwiboo.se>,
        Jernej Skrabec <jernej.skrabec@gmail.com>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>,
        dri-devel <dri-devel@lists.freedesktop.org>,
        LKML <linux-kernel@vger.kernel.org>
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On Thu, Aug 18, 2022 at 11:19 AM Rock Chiu
<rock.chiu@paradetech.corp-partner.google.com> wrote:
>
> How does T4/T5  impact the real case? We talked previously the T4/T5
> shouldn't cause user impact.
> Do we have testing data from ODM?
>
Please leave comments below the previous comment's headline.

I'm confused. The reason I upstreamed this patch is because this is in
your application note and you asked us to help upstream it. Now do you
mean that we don't need T4 and T5?

> Rock Chiu
>
> Hsin-Yi Wang <hsinyi@chromium.org> =E6=96=BC 2022=E5=B9=B48=E6=9C=8818=E6=
=97=A5 =E9=80=B1=E5=9B=9B =E4=B8=8A=E5=8D=8810:43=E5=AF=AB=E9=81=93=EF=BC=
=9A
> >
> > On Thu, Aug 18, 2022 at 6:54 AM Doug Anderson <dianders@chromium.org> w=
rote:
> > >
> > > Hi,
> > >
> > > On Mon, Aug 15, 2022 at 2:39 AM Hsin-Yi Wang <hsinyi@chromium.org> wr=
ote:
> > > >
> > > > The double reset power-on sequence is a workaround for the hardware
> > > > flaw in some chip that SPI Clock output glitch and cause internal M=
PU
> > > > unable to read firmware correctly. The sequence is suggested in ps8=
640
> > > > application note.
> > > >
> > > > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> > > > ---
> > > >  drivers/gpu/drm/bridge/parade-ps8640.c | 5 +++++
> > > >  1 file changed, 5 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/d=
rm/bridge/parade-ps8640.c
> > > > index 49107a6cdac18..d7483c13c569b 100644
> > > > --- a/drivers/gpu/drm/bridge/parade-ps8640.c
> > > > +++ b/drivers/gpu/drm/bridge/parade-ps8640.c
> > > > @@ -375,6 +375,11 @@ static int __maybe_unused ps8640_resume(struct=
 device *dev)
> > > >         gpiod_set_value(ps_bridge->gpio_reset, 1);
> > > >         usleep_range(2000, 2500);
> > > >         gpiod_set_value(ps_bridge->gpio_reset, 0);
> > > > +       /* Double reset for T4 and T5 */
> > > > +       msleep(50);
> > > > +       gpiod_set_value(ps_bridge->gpio_reset, 1);
> > > > +       msleep(50);
> > > > +       gpiod_set_value(ps_bridge->gpio_reset, 0);
> > >
> > > We really need another 100 ms here? ps8640 is already quite slow at
> > > powering itself up and that has a real user impact. Why was it only
> > > 2.5 ms for the first reset and 50 ms for the second?
> > >
> >
> > The T4 and T5 are required by Parade. I'm wondering if they can
> > shorten the 200ms below:
> >
> > /*
> > * Mystery 200 ms delay for the "MCU to be ready". It's unclear if
> > * this is truly necessary since the MCU will already signal that
> > * things are "good to go" by signaling HPD on "gpio 9". See
> > * _ps8640_wait_hpd_asserted(). For now we'll keep this mystery delay
> > * just in case.
> > */
> > msleep(200);
> >
> > Does this have to wait 200ms? Can it shorten to 100 due to the
> > additional 100ms from T4 and T5?
> >
> > > -Doug