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From:   <Daire.McNamara@microchip.com>
To:     <heinrich.schuchardt@canonical.com>, <Conor.Dooley@microchip.com>,
        <robh+dt@kernel.org>
CC:     <linux-riscv@lists.infradead.org>,
        <emil.renner.berthing@canonical.com>, <devicetree@vger.kernel.org>,
        <paul.walmsley@sifive.com>, <aou@eecs.berkeley.edu>,
        <palmer@dabbelt.com>, <geert@linux-m68k.org>,
        <linux-kernel@vger.kernel.org>, <stable@vger.kernel.org>,
        <atishp@rivosinc.com>, <krzysztof.kozlowski+dt@linaro.org>
Subject: Re: [PATCH 1/1] riscv: dts: microchip: correct L2 cache interrupts
Thread-Topic: [PATCH 1/1] riscv: dts: microchip: correct L2 cache interrupts
Thread-Index: AQHYsjzjuV6JQqnbNU6bXELDL6GyqK2zYxOAgADZw4A=
Date:   Thu, 18 Aug 2022 07:03:45 +0000
Message-ID: <ccb5792bfe467dcc5046b7cb4de3a6af14cd3d5a.camel@microchip.com>
References: <20220817132521.3159388-1-heinrich.schuchardt@canonical.com>
         <32a72954-c692-6c5d-b07b-266d426c3cb4@microchip.com>
In-Reply-To: <32a72954-c692-6c5d-b07b-266d426c3cb4@microchip.com>
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