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[79.185.51.234]) by smtp.gmail.com with ESMTPSA id p8-20020a2eba08000000b0025df5f38da8sm263859lja.119.2022.08.18.08.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Aug 2022 08:20:12 -0700 (PDT) From: Adam Skladowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/2] Add DISPCC driver for SM6115 Date: Thu, 18 Aug 2022 17:18:19 +0200 Message-Id: <20220818151850.19917-1-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch series introduce support for SM6115 display clock controller, this driver is based on QCM2290 one. Adam Skladowski (2): dt-bindings: clock: add QCOM SM6115 display clock bindings clk: qcom: Add display clock controller driver for SM6115 .../bindings/clock/qcom,dispcc-sm6115.yaml | 88 +++ drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dispcc-sm6115.c | 615 ++++++++++++++++++ .../dt-bindings/clock/qcom,dispcc-sm6115.h | 36 + 5 files changed, 749 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm6115.yaml create mode 100644 drivers/clk/qcom/dispcc-sm6115.c create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm6115.h -- 2.25.1