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[2620:137:e000::1:20]) by mx.google.com with ESMTP id f123-20020a636a81000000b0042a3acb5b15si196642pgc.267.2022.08.18.13.00.24; Thu, 18 Aug 2022 13:00:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@lunn.ch header.s=20171124 header.b=xarjqNzN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344979AbiHRTw3 (ORCPT + 99 others); Thu, 18 Aug 2022 15:52:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242745AbiHRTw1 (ORCPT ); Thu, 18 Aug 2022 15:52:27 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F5E19A97C; Thu, 18 Aug 2022 12:52:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Transfer-Encoding:Content-Disposition: Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:From: Sender:Reply-To:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Content-Disposition: In-Reply-To:References; bh=3h1hpF2gVXT4E0fClqlbNqbC6Ysb7gES9vj8YGM41WM=; b=xa rjqNzN7eVwSKe+eVpuEXGFj62YX5OAzJPYy4WC4jfTdyAa/O05qYnoI88g5B1xvI54kVDQuI3jct8 ztXwqU0y7fgSfNpFoQBuQdFDddlorMpshWZ2RvEGio5/q/zDILZ8M5w5EsyKH8IA3eshRYW8Duj7a 78wjcQOxjKBqYRM=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1oOlYx-00Dpsg-SD; Thu, 18 Aug 2022 21:52:19 +0200 Date: Thu, 18 Aug 2022 21:52:19 +0200 From: Andrew Lunn To: Pali =?iso-8859-1?Q?Roh=E1r?= Cc: Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Rob Herring , Sebastian Hesselbarth , Gregory Clement , Thomas Petazzoni , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 4/4] ARM: dts: dove: Add definitions for PCIe error interrupts Message-ID: References: <20220817230036.817-1-pali@kernel.org> <20220817230036.817-5-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220817230036.817-5-pali@kernel.org> X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Aug 18, 2022 at 01:00:36AM +0200, Pali Roh?r wrote: > First PCIe controller on Dove SoC reports error interrupt via IRQ 15 > and second PCIe controller via IRQ 17. > > Signed-off-by: Pali Roh?r Reviewed-by: Andrew Lunn Andrew