Received: by 2002:a05:6358:4e97:b0:b3:742d:4702 with SMTP id ce23csp1122788rwb; Thu, 18 Aug 2022 19:56:52 -0700 (PDT) X-Google-Smtp-Source: AA6agR62TZG/rwvmqb1dbfZWdOnOKanrZxYkVwPUkMUrBhMWFaxUaTmkmRabPcOl9Eos21ihdxMN X-Received: by 2002:a05:6402:916:b0:440:9bc5:da7a with SMTP id g22-20020a056402091600b004409bc5da7amr4308134edz.323.1660877812536; Thu, 18 Aug 2022 19:56:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660877812; cv=none; d=google.com; s=arc-20160816; b=FwhrYAlcrrpegaRjDiQy29Jwtc8n6hpDoq3qNgpDyuU5+O00/6umD3D17SJWhc5RIr YCZOt8N2S/gVh9gc8wXtwqLjp4MfUO7BBVPjhJzjLqoqykr095ArVF/fmKEUa7tkJMxF eAU4Hlat2pZD3RSUITp8/UHzR5gWAAAL5vIw7xWQQpM+oVlzkwoaDBePS7XbO2cyZ3DQ VZb0gzqairAIFDPtJ9O8UFM6oD6qR3yAi6vbX/xOvvxGh9QTfNThrbISe0fw+Q7K61i5 INEzKCaOkYdTQ7W7+OI7TLxfZQZVS/2Q6wDh+yJgU6nZCeh8K+5vbIRQRwRk3k2wbZef M/nA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:user-agent:message-id:in-reply-to :date:references:subject:cc:to:from:dkim-signature; bh=pStcOB0QkWK/tPWxuZpYhJ7/Bl+mnqTupKxIt1KHY/U=; b=pvHeZgDTk2+7a/SKNe1Pp2ZIRAxPx8ZCwjEgHEcDHpk5E8mnJmywV62LCokdPelXGx /q8si95fH1svzoXUkndGfGvRk3eBltqtzaDRo40jtomGhKywQKY7YBqY6kfnmXANFi8M 0n9kjpGhMwZDHFyU4uhW+uvJwm5+FTKtv7c/7oaExIZDEZLISYQUVb2pqc1v/39viJ8v yKLvEA+SnDnbcII6IjCpRew0H/UCB2Uo5imFikdQlxqQjgiJXnF4MbxZLG7Oc0dqmqhE LofkblpnDEGeTmOSDZS4adRF6YMH8libdXZ0nAvwOjc4+21M2bMfk0CLHHHIg6nIsd3T ZeYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="MAQm/qzG"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id wg6-20020a17090705c600b0072b4adf5c0fsi2364451ejb.77.2022.08.18.19.56.26; Thu, 18 Aug 2022 19:56:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="MAQm/qzG"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344795AbiHSCvh (ORCPT + 99 others); Thu, 18 Aug 2022 22:51:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344394AbiHSCvg (ORCPT ); Thu, 18 Aug 2022 22:51:36 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F434CCE08; Thu, 18 Aug 2022 19:51:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660877495; x=1692413495; h=from:to:cc:subject:references:date:in-reply-to: message-id:mime-version; bh=4EIcg7RWk2yRi+CSvUOFGKBdAdmQg2lkeFcyyl4c1Jg=; b=MAQm/qzGZtALfQNlgWU4xhzpIPSCxEXsgws/OH7C6edZHdhPXSVo3UkL eaftOK38EVbj47t9BOOJbkZMnpqnpkswckM1iUs9BqgRcU/O3vBlPc2Xj nbjrsqpBRae9qddYqLO26yfh7GsUw2qM4vmVXlY6n1aro/IE936El9PYA mNc9jlz5OjbbUQ59SBO/zMKN7rABbtf+79FcCMwioDMNflaeAR00yjJpq y5FMDdkc9dQt9EX55Hr6TWHcFpXLzybpJdjkl+w36c0nRu78ySSt6BR5W OnhEv9VgwuaoIZmzXjkBxaJh/Fv5jX+NgznhBEETOg/W0ClCOpSuCsu04 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10443"; a="275964302" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275964302" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 19:51:34 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="936054349" Received: from yhuang6-desk2.sh.intel.com (HELO yhuang6-desk2.ccr.corp.intel.com) ([10.238.208.55]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 19:51:29 -0700 From: "Huang, Ying" To: Peter Xu Cc: Nadav Amit , Alistair Popple , huang ying , Linux MM , Andrew Morton , LKML , "Sierra Guiza, Alejandro (Alex)" , Felix Kuehling , Jason Gunthorpe , John Hubbard , David Hildenbrand , Ralph Campbell , Matthew Wilcox , Karol Herbst , Lyude Paul , Ben Skeggs , Logan Gunthorpe , paulus@ozlabs.org, linuxppc-dev@lists.ozlabs.org, stable@vger.kernel.org Subject: Re: [PATCH v2 1/2] mm/migrate_device.c: Copy pte dirty bit to page References: <6e77914685ede036c419fa65b6adc27f25a6c3e9.1660635033.git-series.apopple@nvidia.com> <871qtfvdlw.fsf@nvdebian.thelocal> <87o7wjtn2g.fsf@nvdebian.thelocal> <87tu6bbaq7.fsf@yhuang6-desk2.ccr.corp.intel.com> <1D2FB37E-831B-445E-ADDC-C1D3FF0425C1@gmail.com> <87czcyawl6.fsf@yhuang6-desk2.ccr.corp.intel.com> Date: Fri, 19 Aug 2022 10:51:27 +0800 In-Reply-To: (Peter Xu's message of "Thu, 18 Aug 2022 10:44:46 -0400") Message-ID: <874jy9aqts.fsf@yhuang6-desk2.ccr.corp.intel.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=ascii X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Peter Xu writes: > On Thu, Aug 18, 2022 at 02:34:45PM +0800, Huang, Ying wrote: >> > In this specific case, the only way to do safe tlb batching in my mind is: >> > >> > pte_offset_map_lock(); >> > arch_enter_lazy_mmu_mode(); >> > // If any pending tlb, do it now >> > if (mm_tlb_flush_pending()) >> > flush_tlb_range(vma, start, end); >> > else >> > flush_tlb_batched_pending(); >> >> I don't think we need the above 4 lines. Because we will flush TLB >> before we access the pages. > > Could you elaborate? As you have said below, we don't use non-present PTEs and flush present PTEs before we access the pages. >> Can you find any issue if we don't use the above 4 lines? > > It seems okay to me to leave stall tlb at least within the scope of this > function. It only collects present ptes and flush propoerly for them. I > don't quickly see any other implications to other not touched ptes - unlike > e.g. mprotect(), there's a strong barrier of not allowing further write > after mprotect() returns. Yes. I think so too. > Still I don't know whether there'll be any side effect of having stall tlbs > in !present ptes because I'm not familiar enough with the private dev swap > migration code. But I think having them will be safe, even if redundant. I don't think it's a good idea to be redundant. That may hide the real issue. Best Regards, Huang, Ying