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[2620:137:e000::1:20]) by mx.google.com with ESMTP id j36-20020a63fc24000000b0040dd4d169a3si3448104pgi.858.2022.08.19.01.59.45; Fri, 19 Aug 2022 01:59:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=aOTMyLcG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347912AbiHSI6W (ORCPT + 99 others); Fri, 19 Aug 2022 04:58:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347270AbiHSI6L (ORCPT ); Fri, 19 Aug 2022 04:58:11 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8C54EF038; Fri, 19 Aug 2022 01:58:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660899490; x=1692435490; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ziIKS5pUN4XvJWFDzWjnZe0+IpFs3iXynkoSh+5gFuY=; b=aOTMyLcGzX07W39dEPW7wOPe07qj9eoG78pmGajSFDlG0ia3O6hkPro5 U58wjrugCVcETn+OWgEuGj4Ox3WNt+9jEZTPODExCKHYd/oRO6EWctBOd 3mieYu+Sa8Xh7QSqidj0A+1l5VB4lZHk8bDuovNsu/d2TEhPvUlmB97Fd r3TNmzgdMqjABsslJtYuCbcXwl0sKFPOFgNmq+YQZ0zPtN+L2pK8gtoTg sZBysUlkv4G6HHSh3IAfoy5j77efL85/qhhIamiGc1JARfy/Aq4fK7Ded 08qAukXAIwUocMC0Dz0f//7guKIVhyaNMy6WiWH4Fa6tNy+cuF0mDlxD/ A==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="170004569" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 01:58:09 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 01:58:08 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 01:58:06 -0700 From: Conor Dooley To: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Rob Herring" , Krzysztof Kozlowski CC: Daire McNamara , , , , , Conor Dooley , Rob Herring Subject: [PATCH v9 1/4] dt-bindings: pwm: fix microchip corePWM's pwm-cells Date: Fri, 19 Aug 2022 09:57:01 +0100 Message-ID: <20220819085703.4161266-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220819085703.4161266-1-conor.dooley@microchip.com> References: <20220819085703.4161266-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org corePWM is capable of inverted operation but the binding requires \#pwm-cells of 2. Expand the binding to support setting the polarity. Fixes: df77f7735786 ("dt-bindings: pwm: add microchip corepwm binding") Acked-by: Rob Herring Acked-by: Uwe Kleine-König Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml index a7fae1772a81..cd8e9a8907f8 100644 --- a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml +++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml @@ -30,7 +30,9 @@ properties: maxItems: 1 "#pwm-cells": - const: 2 + enum: [2, 3] + description: + The only flag supported by the controller is PWM_POLARITY_INVERTED. microchip,sync-update-mask: description: | -- 2.36.1