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Date:   Fri, 19 Aug 2022 20:19:43 +0200
From:   Marek =?UTF-8?B?QmVow7pu?= <kabel@kernel.org>
To:     Marcus Carlberg <marcus.carlberg@axis.com>
Cc:     Andrew Lunn <andrew@lunn.ch>,
        Vivien Didelot <vivien.didelot@gmail.com>,
        Florian Fainelli <f.fainelli@gmail.com>,
        Vladimir Oltean <olteanv@gmail.com>,
        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>, <kernel@axis.com>,
        <netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] net: dsa: mv88e6xxx: support RGMII cmode
Message-ID: <20220819201943.5f6a4d09@thinkpad>
In-Reply-To: <20220819135629.32590-1-marcus.carlberg@axis.com>
References: <20220819135629.32590-1-marcus.carlberg@axis.com>
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On Fri, 19 Aug 2022 15:56:29 +0200
Marcus Carlberg <marcus.carlberg@axis.com> wrote:

> Since the probe defaults all interfaces to the highest speed possible
> (10GBASE-X in mv88e6393x) before the phy mode configuration from the
> devicetree is considered it is currently impossible to use port 0 in
> RGMII mode.
> 
> This change will allow RGMII modes to be configurable for port 0
> enabling port 0 to be configured as RGMII as well as serial depending
> on configuration.
> 
> Signed-off-by: Marcus Carlberg <marcus.carlberg@axis.com>
> ---
> 
> Notes:
>     v2: add phy mode input validation for SERDES only ports
> 
>  drivers/net/dsa/mv88e6xxx/port.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
> index 90c55f23b7c9..5c4195c635b0 100644
> --- a/drivers/net/dsa/mv88e6xxx/port.c
> +++ b/drivers/net/dsa/mv88e6xxx/port.c
> @@ -517,6 +517,12 @@ static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
>  	case PHY_INTERFACE_MODE_RMII:
>  		cmode = MV88E6XXX_PORT_STS_CMODE_RMII;
>  		break;
> +	case PHY_INTERFACE_MODE_RGMII:
> +	case PHY_INTERFACE_MODE_RGMII_ID:
> +	case PHY_INTERFACE_MODE_RGMII_RXID:
> +	case PHY_INTERFACE_MODE_RGMII_TXID:
> +		cmode = MV88E6XXX_PORT_STS_CMODE_RGMII;
> +		break;
>  	case PHY_INTERFACE_MODE_1000BASEX:
>  		cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX;
>  		break;
> @@ -634,6 +640,19 @@ int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
>  	if (port != 0 && port != 9 && port != 10)
>  		return -EOPNOTSUPP;
>  
> +	if (port == 9 || port == 10) {
> +		switch (mode) {
> +		case PHY_INTERFACE_MODE_RMII:
> +		case PHY_INTERFACE_MODE_RGMII:
> +		case PHY_INTERFACE_MODE_RGMII_ID:
> +		case PHY_INTERFACE_MODE_RGMII_RXID:
> +		case PHY_INTERFACE_MODE_RGMII_TXID:
> +			return -EINVAL;
> +		default:
> +			break;
> +		}
> +	}
> +
>  	/* mv88e6393x errata 4.5: EEE should be disabled on SERDES ports */
>  	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
>  	if (err)

You also need to change
 mv88e6393x_phylink_get_caps in chip.c
to add RGMII interface types to the supported bit field if port == 0,
because the mv88e6xxx_translate_cmode() call does not fill RGMII as
supported there if cmode isn't RGMII at the beginning.

Also this should have Fixes tag?

Marek