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[2620:137:e000::1:20]) by mx.google.com with ESMTP id u15-20020a170902e80f00b001729c880321si7271570plg.96.2022.08.20.06.40.11; Sat, 20 Aug 2022 06:40:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=nWKPnQZd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346630AbiHTM6R (ORCPT + 99 others); Sat, 20 Aug 2022 08:58:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346536AbiHTM6H (ORCPT ); Sat, 20 Aug 2022 08:58:07 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AC6372848; Sat, 20 Aug 2022 05:57:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661000272; x=1692536272; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DANL4aKJSy65svgCcuzEytfERDJ+TNEuh4HmxezDpJ8=; b=nWKPnQZdHdEW2QBTHpbq7bWz/YOSWJ4A8kLET5jvxnPTeQ5xFXqdPaRv e76WAH823sz5dFtyU18D40DK9UZWX0Cfl+ViZyvnsHDVbRPoKCPlw1TYZ r0EbRZy3btFYPhPt3L+8p7i70koHPd3pFgNrooXlonvIkUL979ZNzUcOv EZQo87RakDa6tKNYpbkwr0eYrQj/d6fntjw1SgmJHRiOax60Bb03jvypl vvQRwf6VoKwZa5FA4XBHWS6/EwUixHVmHFhlAnfDmTMp67CqtqDZLg+GT 6MCD2jcgYbRejSkt03bNvByjLFoBnPrI7O2ewSTmIccqndw/2xaPXIlyb Q==; X-IronPort-AV: E=Sophos;i="5.93,251,1654585200"; d="scan'208";a="187325452" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Aug 2022 05:57:46 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Sat, 20 Aug 2022 05:57:46 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Sat, 20 Aug 2022 05:57:43 -0700 From: Tudor Ambarus To: , , , CC: , , , , , , , , , , Tudor Ambarus , Subject: [PATCH 07/33] dmaengine: at_hdmac: Fix at_lli struct definition Date: Sat, 20 Aug 2022 15:56:51 +0300 Message-ID: <20220820125717.588722-8-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220820125717.588722-1-tudor.ambarus@microchip.com> References: <20220820125717.588722-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Those hardware registers are all of 32 bits, while dma_addr_t ca be of type u64 or u32 depending on CONFIG_ARCH_DMA_ADDR_T_64BIT. Force u32 to comply with what the hardware expects. Fixes: dc78baa2b90b ("dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller") Signed-off-by: Tudor Ambarus Cc: stable@vger.kernel.org --- drivers/dma/at_hdmac.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index 91e53a590d5f..e89facf14fab 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -187,13 +187,13 @@ /* LLI == Linked List Item; aka DMA buffer descriptor */ struct at_lli { /* values that are not changed by hardware */ - dma_addr_t saddr; - dma_addr_t daddr; + u32 saddr; + u32 daddr; /* value that may get written back: */ - u32 ctrla; + u32 ctrla; /* more values that are not changed by hardware */ - u32 ctrlb; - dma_addr_t dscr; /* chain to next lli */ + u32 ctrlb; + u32 dscr; /* chain to next lli */ }; /** -- 2.25.1