Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
MIME-Version: 1.0
References: <20220815093905.134164-1-hsinyi@chromium.org> <CAD=FV=XYNKF8q1mttru_J188pYMjSphQsEfQAO1Bt7GvjJRKXw@mail.gmail.com>
 <CAJMQK-gjg9evLY3oP5rgaGoRdQQTLqnK2-FChaabJTCxLTTmYA@mail.gmail.com>
 <CAMuczyUH1tefU_4+dx495_5kdrxRdA3pmXS-eyjzMCcYFfjNXQ@mail.gmail.com>
 <CAJMQK-jEgRq68JXSWtS4y5_39vJ1pWCT2-Atg31__veRtnuREA@mail.gmail.com> <CAD=FV=UXFiA4hW8_cmO0Di-NCpqvkjTqqOfbc6DfD5Rs8aT6hA@mail.gmail.com>
In-Reply-To: <CAD=FV=UXFiA4hW8_cmO0Di-NCpqvkjTqqOfbc6DfD5Rs8aT6hA@mail.gmail.com>
From:   Doug Anderson <dianders@chromium.org>
Date:   Mon, 22 Aug 2022 09:33:00 -0700
Message-ID: <CAD=FV=Vg5o-OxyQnemB+XfkGundDA-R31QhkmHJv4RmTMcF2gA@mail.gmail.com>
Subject: Re: [PATCH] drm/bridge: ps8640: Add double reset T4 and T5 to
 power-on sequence
To:     Hsin-Yi Wang <hsinyi@chromium.org>
Cc:     Rock Chiu <rock.chiu@paradetech.corp-partner.google.com>,
        Andrzej Hajda <andrzej.hajda@intel.com>,
        Neil Armstrong <narmstrong@baylibre.com>,
        Robert Foss <robert.foss@linaro.org>,
        Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
        Jonas Karlman <jonas@kwiboo.se>,
        Jernej Skrabec <jernej.skrabec@gmail.com>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>,
        dri-devel <dri-devel@lists.freedesktop.org>,
        LKML <linux-kernel@vger.kernel.org>
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

Hi,

On Thu, Aug 18, 2022 at 8:03 AM Doug Anderson <dianders@chromium.org> wrote:
>
> Hi,
>
> On Wed, Aug 17, 2022 at 8:22 PM Hsin-Yi Wang <hsinyi@chromium.org> wrote:
> >
> > On Thu, Aug 18, 2022 at 11:19 AM Rock Chiu
> > <rock.chiu@paradetech.corp-partner.google.com> wrote:
> > >
> > > How does T4/T5  impact the real case? We talked previously the T4/T5
> > > shouldn't cause user impact.
> > > Do we have testing data from ODM?
> > >
> > Please leave comments below the previous comment's headline.
> >
> > I'm confused. The reason I upstreamed this patch is because this is in
> > your application note and you asked us to help upstream it. Now do you
> > mean that we don't need T4 and T5?
>
> I think Rock is asking what problems the extra delay is causing. In
> other words: why do we care about keeping these delays short?
>
> The answer is that it affects boot speed and also resume speed of
> devices. Adding these two delays here means that there's an extra 100
> ms before the user can see something on the screen. That may not seem
> like a lot, but those kinds of delays add up quickly. At least on
> Chromebooks, booting quickly is always a big goal.

While I'm not very happy with this change and I don't really
understand why these delays need to be so long, if folks are really
certain that we need them and can't make them shorter then I guess we
can land it. I'll wait a few more days in case anyone wants to chime
in with their thoughts.

-Doug