Received: by 2002:a05:6358:5282:b0:b5:90e7:25cb with SMTP id g2csp2679272rwa; Mon, 22 Aug 2022 11:38:16 -0700 (PDT) X-Google-Smtp-Source: AA6agR40B+Mt9Yloodeh7zew2NOZ6E38gd5O/MvqeYOPQf0TI2wLa39avUsji0FlG049kQsQ+s2G X-Received: by 2002:a05:6a00:a8f:b0:530:3c05:4644 with SMTP id b15-20020a056a000a8f00b005303c054644mr22235763pfl.79.1661193496218; Mon, 22 Aug 2022 11:38:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1661193496; cv=none; d=google.com; s=arc-20160816; b=IlzOnjKareffewof3K8T1eHW7Se0Y6EPcg+u38CgVjwWr2e5M/9yNQ9l2qKxZRMiTY hbw7eFXKZoSzIuox8Qi7YrSityns98W+SXShll0CyeIMTPIsVU0ETBzbQz/6WGYejdzS tFf4h/wzrIFwJZ9oyBtUiR/D16o+LpGmUdecpDQHmQRBIOqLa6pf9FsHGlIo3g7OcFju v502B+uOAuIDgKXSKO+3jKPAmgymVDfldSWmP2uKzHTOlRy0ytKY6eYvT+d44jUctUR8 q/gRHPt6nKhirUPTXLQjo/itdcMFPgMU6obO+gd7VPo3KjaPnWAo481iitK2aHBTALLM E4Kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:to:from:dkim-signature; bh=/4M0OWf9/1cj1xP6lpI5wF75FEHgNvyYms0c6exL/JA=; b=FaoArhZzyoe2ug9L9Ofn513J0LKvZ+3HwKx0HJulauiDyBwsU6SmuAd1CrXYWOgUYM UyiUCHOpsDQjbzHcd2InMeW1lqs367PqIluSnIrbEtXKkdrZd/2TlAGKQvRiLifU121W dnD4Ex0ZHdZ6/dCHkdxDVOHvjqLbHgQhGfk23Q35560X9N1wk+WiTgz39HKpLu7Qpuib YLBQE/em+TF30H/gG2zby+qvi/hZCniCb1Y5wPSfZgLppmGTS7wqzvGtuIhuqCR+s3zq BiOfsJ1XwzpYKp96QrQbTB1aLHNfcCnkltdrzgSOlP1ZPjR3lrcT52LEyh4NQc6U6mh9 TStQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=cToE3MLI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k201-20020a6284d2000000b00535fc5e755dsi11581797pfd.82.2022.08.22.11.38.04; Mon, 22 Aug 2022 11:38:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=cToE3MLI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236954AbiHVSNf (ORCPT + 99 others); Mon, 22 Aug 2022 14:13:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236960AbiHVSNc (ORCPT ); Mon, 22 Aug 2022 14:13:32 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FC95FD3F; Mon, 22 Aug 2022 11:13:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661192011; x=1692728011; h=from:to:subject:date:message-id:in-reply-to:references: mime-version; bh=vZuRmNuSCtdwbDpyBHx5Qp3L/RMLonq82mslgVMRybA=; b=cToE3MLI9+xLs81sG8P5nKRcSNLHyR2Y0MoGgfyBveQ9IEd4puHQw6uo iJJWyDpdSvEYSA9I5nMv50mF9xRP6PA412m/T8bTYgcBF28NyH66IHUud SW/3S6Kk0wmzbKMBwy/OMxLwQwnMKviNBSuP3cFRyg3cQnhXtF2riJ3ri ESl9POrEF9DcKpBNMWWxwzz5JfewrmJkrO9vMmwuNU51QvIAHUEwkpgPV GsnRuRA0+R13xLgZzjoAu0KKNBLNABaAc4TFf4hGooedsoI8u4yc5J3xK zC62VMwz47zcMj7fV8iXO65jezZ37e/Mjm5nfsTS23Cst6VhQBvEIBkc7 Q==; X-IronPort-AV: E=Sophos;i="5.93,255,1654585200"; d="scan'208";a="187555683" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Aug 2022 11:13:28 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 22 Aug 2022 11:13:18 -0700 Received: from AUS-LT-C33025.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 22 Aug 2022 11:13:16 -0700 From: Jerry Ray To: Rob Herring , Nicolas Ferre , Alexandre Belloni , Ludovic Desroches , , , , "Jerry Ray" Subject: [linux][PATCH v2 2/2] dts: arm: at91: Add SAMA5D3-EDS Board Date: Mon, 22 Aug 2022 13:13:14 -0500 Message-ID: <20220822181314.8325-2-jerry.ray@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220822181314.8325-1-jerry.ray@microchip.com> References: <20220822181314.8325-1-jerry.ray@microchip.com> MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The SAMA5D3-EDS board is an Ethernet Development Platform allowing for evaluating many Microchip ethernet switch and PHY products. Various daughter cards can connect up via an RGMII connector or an RMII connector. The EDS board is not intended for stand-alone use and has no ethernet capabilities when no daughter board is connected. As such, this device tree is intended to be used with a DT overlay defining the add-on board. To better ensure consistency, some items are defined here as a form of documentation so that all add-on overlays will use the same terms. Google search keywords: "Microchip SAMA5D3-EDS" Signed-off-by: Jerry Ray --- v1->v2: - Modified the compatible field in the device tree to reflect Microchip Ethernet Development System Board. --- arch/arm/boot/dts/at91-sama5d3_eds.dts | 314 +++++++++++++++++++++++++ 1 file changed, 314 insertions(+) create mode 100644 arch/arm/boot/dts/at91-sama5d3_eds.dts diff --git a/arch/arm/boot/dts/at91-sama5d3_eds.dts b/arch/arm/boot/dts/at91-sama5d3_eds.dts new file mode 100644 index 000000000000..626f7bbe0164 --- /dev/null +++ b/arch/arm/boot/dts/at91-sama5d3_eds.dts @@ -0,0 +1,314 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91-sama5d3_eds.dts - Device Tree file for the SAMA5D3 Ethernet + * Development System board. + * + * Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries + * 2022 Jerry Ray + */ +/dts-v1/; +#include "sama5d36.dtsi" + +/ { + model = "SAMA5D3 Ethernet Development System"; + compatible = "microchip,sama5d3-eds", "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + button-3 { + label = "PB_USER"; + gpios = <&pioE 29 GPIO_ACTIVE_LOW>; + linux,code = <0x104>; + wakeup-source; + }; + }; + + memory@20000000 { + reg = <0x20000000 0x10000000>; + }; + + regulators: regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vcc_3v3_reg: BUCK_REG1 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_2v5_reg: LDO_REG2 { + compatible = "regulator-fixed"; + regulator-name = "VCC_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + vin-supply = <&vcc_3v3_reg>; + }; + + vcc_1v8_reg: LDO_REG3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vcc_3v3_reg>; + }; + + vcc_1v2_reg: BUCK_REG4 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_mmc0_reg: fixedregulator_mmc0 { + compatible = "regulator-fixed"; + regulator-name = "mmc0-card-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_mmc0_reg_gpio>; + gpio = <&pioE 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&can0 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + }; +}; + +&i2c0 { + pinctrl-0 = <&pinctrl_i2c0_pu>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + dmas = <0>, <0>; /* Do not use DMA for i2c2 */ + pinctrl-0 = <&pinctrl_i2c2_pu>; + status = "okay"; +}; + +&mmc0 { + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 + &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; + vmmc-supply = <&vcc_mmc0_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <8>; + cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + board { + pinctrl_i2c0_pu: i2c0_pu { + atmel,pins = + , + ; + }; + + pinctrl_i2c2_pu: i2c2_pu { + atmel,pins = + , + ; + }; + + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + ; + }; + + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = + ; + }; + + pinctrl_spi0_cs: spi0_cs_default { + atmel,pins = + ; + }; + + pinctrl_spi1_cs: spi1_cs_default { + atmel,pins = ; + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; + }; + + pinctrl_usb_default: usb_default { + atmel,pins = + ; + }; + + pinctrl_vcc_mmc0_reg_gpio: vcc_mmc0_reg_gpio_default { + atmel,pins = ; + }; + + /* Reserved for reset signal to the RGMII connector. */ + pinctrl_rgmii_rstn: rgmii_rstn { + atmel,pins = + ; + }; + + /* Reserved for an interrupt line from the RMII and RGMII connectors. */ + pinctrl_spi_irqn: spi_irqn { + atmel,pins = + ; + }; + + /* Reserved for VBUS fault interrupt. */ + pinctrl_vbusfault_irqn: vbusfault_irqn { + atmel,pins = + ; + }; + }; +}; + +&spi0 { + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi0_cs>; + cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi1_cs>; + cs-gpios = <&pioC 25 0>, <0>, <0>, <&pioC 28 0>; + status = "okay"; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&usb0 { + atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + +&usb1 { + atmel,vbus-gpio = <0 + &pioE 3 GPIO_ACTIVE_HIGH + &pioE 4 GPIO_ACTIVE_HIGH + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + num-ports = <3>; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; -- 2.17.1