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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id f30-20020a056870899e00b00108b31bf8fbsm3183119oaq.53.2022.08.22.14.53.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 14:53:50 -0700 (PDT) Received: (nullmailer pid 923856 invoked by uid 1000); Mon, 22 Aug 2022 21:53:49 -0000 Date: Mon, 22 Aug 2022 16:53:49 -0500 From: Rob Herring To: Conor.Dooley@microchip.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mturquette@baylibre.com, linux-riscv@lists.infradead.org, palmer@dabbelt.com, sboyd@kernel.org, aou@eecs.berkeley.edu, Hugh.Breslin@microchip.com, krzysztof.kozlowski+dt@linaro.org, paul.walmsley@sifive.com, linux-clk@vger.kernel.org, Daire.McNamara@microchip.com Subject: Re: [PATCH v2 2/6] dt-bindings: clk: document PolarFire SoC fabric clocks Message-ID: <20220822215349.GA913400-robh@kernel.org> References: <20220822112928.2727437-1-conor.dooley@microchip.com> <20220822112928.2727437-3-conor.dooley@microchip.com> <1661197242.557172.413609.nullmailer@robh.at.kernel.org> <92e15fa9-65f4-1dea-48eb-f3afbea5d3f4@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <92e15fa9-65f4-1dea-48eb-f3afbea5d3f4@microchip.com> X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Aug 22, 2022 at 07:44:20PM +0000, Conor.Dooley@microchip.com wrote: > On 22/08/2022 20:40, Rob Herring wrote: > > On Mon, 22 Aug 2022 12:29:25 +0100, Conor Dooley wrote: > >> On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the > >> ordinal corners of the chip, which our documentation refers to as > >> "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are > >> highly configurable & many of the input clocks are optional. > >> > >> Signed-off-by: Conor Dooley > >> --- > >> .../bindings/clock/microchip,mpfs-ccc.yaml | 81 +++++++++++++++++++ > >> 1 file changed, 81 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml > >> > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > Heh, been waiting for this one all day. Messed up squashing commits > before sending v2... fixed locally & I'll respin later in the week. > I tried to mark it "changes required" in patchwork so you'd not waste > time on it but I think that got reverted? Could have. The CI job messes with the state and then I do, and my scripts don't expect the state changing underneath it. Most users don't have PW accounts. Don't worry, I don't spend much time on failing patches. Rob