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Date:   Tue, 23 Aug 2022 16:31:35 +0200
From:   Alexander 'lynxis' Couzens <lynxis@fe80.eu>
To:     Paolo Abeni <pabeni@redhat.com>
Cc:     Felix Fietkau <nbd@nbd.name>, John Crispin <john@phrozen.org>,
        Sean Wang <sean.wang@mediatek.com>,
        Mark Lee <Mark-MC.Lee@mediatek.com>,
        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        Russell King <linux@armlinux.org.uk>, netdev@vger.kernel.org,
        linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
        Daniel Golle <daniel@makrotopia.org>
Subject: Re: [PATCH 1/4] net: mediatek: sgmii: fix powering up the SGMII phy
Message-ID: <20220823163135.013ec257@javelin>
In-Reply-To: <6f147fbd31980c6155ea6e7deba26d8210ed6afd.camel@redhat.com>
References: <20220820224538.59489-1-lynxis@fe80.eu>
        <20220820224538.59489-2-lynxis@fe80.eu>
        <6f147fbd31980c6155ea6e7deba26d8210ed6afd.camel@redhat.com>
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Hi Paolo,

> On Sun, 2022-08-21 at 00:45 +0200, Alexander Couzens wrote:
> > There are cases when the SGMII_PHYA_PWD register contains 0x9 which
> > prevents SGMII from working. The SGMII still shows link but no
> > traffic can flow. Writing 0x0 to the PHYA_PWD register fix the
> > issue. 0x0 was taken from a good working state of the SGMII
> > interface.  
> 
> do you have access to register documentation? what does 0x9 actually
> mean? is the '0' value based on just empirical evaluation?

I don't have any documentation which describes 0x9.
The datasheet [1] only contains the PHYA_PWD (0x10) bit and the initial
value is 0x10. 0x0 value is based on a register readout without the
patch from a working state.

I've tested it on mt7622 and Daniel Golle on mt7986.

[1] MT7622 Reference Manual, v1.0, 2018-12-19, 1972 pages

Best,
lynxis