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[34.168.104.7]) by smtp.gmail.com with ESMTPSA id s19-20020a635253000000b0040d75537824sm5072135pgl.86.2022.08.23.08.40.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Aug 2022 08:40:44 -0700 (PDT) Date: Tue, 23 Aug 2022 15:40:40 +0000 From: Sean Christopherson To: Binbin Wu Cc: isaku.yamahata@intel.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sagi Shahar Subject: Re: [PATCH v8 018/103] KVM: TDX: Stub in tdx.h with structs, accessors, and VMCS helpers Message-ID: References: <651c33a5-4b9b-927f-cb04-ec20b8c3d730@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <651c33a5-4b9b-927f-cb04-ec20b8c3d730@linux.intel.com> X-Spam-Status: No, score=-14.5 required=5.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, ENV_AND_HDR_SPF_MATCH,FSL_HELO_FAKE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,USER_IN_DEF_DKIM_WL,USER_IN_DEF_SPF_WL autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 23, 2022, Binbin Wu wrote: > > On 2022/8/8 6:01, isaku.yamahata@intel.com wrote: > > +static __always_inline void tdvps_vmcs_check(u32 field, u8 bits) > > +{ > > + BUILD_BUG_ON_MSG(__builtin_constant_p(field) && (field) & 0x1, > > + "Read/Write to TD VMCS *_HIGH fields not supported"); > > + > > + BUILD_BUG_ON(bits != 16 && bits != 32 && bits != 64); > > + > > + BUILD_BUG_ON_MSG(bits != 64 && __builtin_constant_p(field) && > > + (((field) & 0x6000) == 0x2000 || > > + ((field) & 0x6000) == 0x6000), > > + "Invalid TD VMCS access for 64-bit field"); > > if bits is 64 here, "bits != 64" is false, how could this check for "Invalid > TD VMCS access for 64-bit field"? Bits 14:13 of the encoding, which is extracted by "(field) & 0x6000", encodes the width of the VMCS field. Bit 0 of the encoding, "(field) & 0x1" above, is a modifier that is only relevant when operating in 32-bit mode, and is disallowed because TDX is 64-bit only. This yields four possibilities for TDX: (field) & 0x6000) == 0x0000 : 16-bit field (field) & 0x6000) == 0x2000 : 64-bit field (field) & 0x6000) == 0x4000 : 32-bit field (field) & 0x6000) == 0x6000 : 64-bit field (technically "natural width", but effectively 64-bit because TDX is 64-bit only) The assertion is that if the encoding indicates a 64-bit field (0x2000 or 0x6000), then the number of bits KVM is accessing must be '64'. The below assertions do the same thing for 32-bit and 16-bit fields. > > + BUILD_BUG_ON_MSG(bits != 32 && __builtin_constant_p(field) && > > + ((field) & 0x6000) == 0x4000, > > + "Invalid TD VMCS access for 32-bit field"); > > ditto > > > > + BUILD_BUG_ON_MSG(bits != 16 && __builtin_constant_p(field) && > > + ((field) & 0x6000) == 0x0000, > > + "Invalid TD VMCS access for 16-bit field"); > > ditto