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Message-ID: <3d052733-3600-b6eb-baf3-d8806a150af3@quicinc.com>
Date:   Wed, 24 Aug 2022 09:07:59 +0530
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Subject: Re: [PATCH v5 2/3] PCI: qcom: Restrict pci transactions after pci
 suspend
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To:     Stephen Boyd <swboyd@chromium.org>, <helgaas@kernel.org>
CC:     <linux-pci@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <mka@chromium.org>,
        <quic_vbadigan@quicinc.com>, <quic_hemantk@quicinc.com>,
        <quic_nitegupt@quicinc.com>, <quic_skananth@quicinc.com>,
        <quic_ramkri@quicinc.com>, <manivannan.sadhasivam@linaro.org>,
        <dmitry.baryshkov@linaro.org>, Jingoo Han <jingoohan1@gmail.com>,
        "Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        Rob Herring <robh@kernel.org>,
        =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= <kw@linux.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Stanimir Varbanov <svarbanov@mm-sol.com>
References: <1659526134-22978-1-git-send-email-quic_krichai@quicinc.com>
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 <CAE-0n500y-n+ZjasYQRAa3JgamQG1c+Aqn0YiX-i0L-w6C4dbQ@mail.gmail.com>
From:   Krishna Chaitanya Chundru <quic_krichai@quicinc.com>
In-Reply-To: <CAE-0n500y-n+ZjasYQRAa3JgamQG1c+Aqn0YiX-i0L-w6C4dbQ@mail.gmail.com>
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On 8/9/2022 12:42 AM, Stephen Boyd wrote:
> Quoting Krishna chaitanya chundru (2022-08-03 04:28:53)
>> If the endpoint device state is D0 and irq's are not freed, then
>> kernel try to mask interrupts in system suspend path by writing
>> in to the vector table (for MSIX interrupts) and config space (for MSI's).
>>
>> These transactions are initiated in the pm suspend after pcie clocks got
>> disabled as part of platform driver pm  suspend call. Due to it, these
>> transactions are resulting in un-clocked access and eventually to crashes.
> Why are the platform driver pm suspend calls disabling clks that early?
> Can they disable clks in noirq phase, or even later, so that we don't
> have to check if the device is clocking in the irq poking functions?
> It's best to keep irq operations fast, so that irq control is fast given
> that these functions are called from irq flow handlers.

We are registering the pcie pm suspend ops as noirq ops only. And this 
msix and config

access is coming at the later point of time that is reason we added that 
check.