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Wed, 24 Aug 2022 10:05:54 +0000 Received: from AM6PR04MB6053.eurprd04.prod.outlook.com ([fe80::6cd5:f11c:4e5c:d79c]) by AM6PR04MB6053.eurprd04.prod.outlook.com ([fe80::6cd5:f11c:4e5c:d79c%3]) with mapi id 15.20.5546.022; Wed, 24 Aug 2022 10:05:54 +0000 From: "Alice Guo (OSS)" To: Marco Felsch CC: Guenter Roeck , "wim@linux-watchdog.org" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "festevam@gmail.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , dl-linux-imx , "kernel@pengutronix.de" , "linux-watchdog@vger.kernel.org" Subject: RE: [PATCH 2/7] watchdog: imx7ulp: Add explict memory barrier for unlock sequence Thread-Topic: [PATCH 2/7] watchdog: imx7ulp: Add explict memory barrier for unlock sequence Thread-Index: AQHYsSoBdxZHPlON40a5XuD6jrx4qK2xDxMAgAmF+ACAAAMHAIAAZZiAgAEFDYCAADtTgIAAMAWAgAEz8ACAABu1AIAACm4AgAAHGQCAAAV54A== Date: Wed, 24 Aug 2022 10:05:54 +0000 Message-ID: References: <20220816062330.z2fvurteg337krw2@pengutronix.de> <20220822080010.ecdphpm3i26cco5f@pengutronix.de> <20220822140347.GA4087281@roeck-us.net> <20220823091027.ezyxkn64asajvjom@pengutronix.de> <20220823120219.GA203169@roeck-us.net> <20220824080338.humjny4fabhmx3z7@pengutronix.de> <20220824090622.ubbuf4doyul7d42r@pengutronix.de> In-Reply-To: <20220824090622.ubbuf4doyul7d42r@pengutronix.de> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6053.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 93e2fe14-e2d9-4161-a8de-08da85b83b79 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Aug 2022 10:05:54.4183 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: g9LV5ZU0AcdqobuG8bnrzsYLUK0VJhIVdaTA9/Hc8J05DGYuXejazUYCbwP1qGEsqECSnZvv0PTjV8/k6hNPfg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR04MB8651 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Marco Felsch > Sent: Wednesday, August 24, 2022 5:06 PM > To: Alice Guo (OSS) > Cc: Guenter Roeck ; wim@linux-watchdog.org; > shawnguo@kernel.org; s.hauer@pengutronix.de; festevam@gmail.com; > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > dl-linux-imx ; kernel@pengutronix.de; > linux-watchdog@vger.kernel.org > Subject: Re: [PATCH 2/7] watchdog: imx7ulp: Add explict memory barrier fo= r > unlock sequence >=20 > Hi Alice, >=20 > On 22-08-24, Alice Guo (OSS) wrote: > > > -----Original Message----- > > > From: Marco Felsch > > > Sent: Wednesday, August 24, 2022 4:04 PM > > > To: Alice Guo (OSS) > > > Cc: Guenter Roeck ; wim@linux-watchdog.org; > > > shawnguo@kernel.org; s.hauer@pengutronix.de; festevam@gmail.com; > > > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > > > dl-linux-imx ; kernel@pengutronix.de; > > > linux-watchdog@vger.kernel.org > > > Subject: Re: [PATCH 2/7] watchdog: imx7ulp: Add explict memory > > > barrier for unlock sequence > > > > > > Hi Alice, > > > > > > On 22-08-24, Alice Guo (OSS) wrote: > > > > > > ... > > > > > > > > > > Hi Guenter and Marco, > > > > > > > > > > > > > > 1. did you see any issues? > > > > > > > This WDOG Timer first appeared in i.MX7ULP, no one report > > > > > > > issues probably because few people use i.MX7ULP. This issue > > > > > > > was found when we did a stress test on it. When we > > > > > > > reconfigure the WDOG Timer, there is a certain probability > > > > > > > that it reset. The reason for the error is that when > > > > > > > WDOG_CS[CMD32EN] is 0, the unlock sequence is two 16-bit > > > > > > > writes (0xC520, 0xD928) to the CNT register within 16 bus > > > > > > > clocks, and improper unlock sequence causes the > > > WDOG to reset. > > > > > > > Adding mb() is to guarantee that two 16-bit writes are > > > > > > > finished within 16 > > > > > bus clocks. > > > > > > > > > > > > After this explanation the whole imx7ulp_wdt_init() seems a > > > > > > bit buggy because writel_relaxed() as well as writel() are > > > > > > 32bit access > > > functions. > > > > > > So the very first thing to do is to enable the 32-bit mode. > > > > > > > > > > > Agreed. This is much better than having extra code to deal with > > > > > both 16-bit and 32-bit access. > > > > > > > > > > > Also this is a explanation worth to be added to the commit > > > > > > message > > > > > > ;) > > > > > > > > > > > > > > > > Definitely. Also, the use of mb(), if it should indeed be > > > > > needed, would have to be explained in a code comment. > > > > > > > > > > Thanks, > > > > > Guenter > > > > > > > > Hi Marco and Guenter, > > > > > > > > Thank you for your comments. I plan to enable support for 32-bit > > > > unlock command write words in bootloader. In this way, there is no > > > > need to distinguish whether the unlock command is a 32-bit command > > > > or a 16-bit command in driver. > > > > > > Please don't move this into the bootloader, enabling it within the > > > init seq. is just fine. If you move it into the bootloader then you > > > can't ensure that the bit is set since there are plenty of bootloader= s out > there. > > > > > > As I said, just drop the "16bit" unlock sequence from the init > > > function because the unlock is handled just fine in all the watchdog_= ops. > > > > > > Regards, > > > Marco > > > > Hi Marco, > > > > Sorry, I did not tell you that all watchdog control bits, timeout > > value, and window value cannot be set until the watchdog is unlocked. >=20 > You don't have to according the RM: > 8<---------------------------------------------------------------------- > 59.5.2 Disable Watchdog after Reset >=20 > All of watchdog registers are unlocked by reset. Therefore, unlock sequen= ce is > unnecessary, but it needs to write all of watchdog registers to make the = new > configuration take effect. The code snippet below shows an example of > disabling watchdog after reset. > 8<---------------------------------------------------------------------- >=20 > also the RM tells us: > 8<---------------------------------------------------------------------- > 59.4.3.1 Configuring the Watchdog Once >=20 > The new configuration takes effect only after all registers except CNT ar= e > written after reset. Otherwise, the WDOG uses the reset values by default= . If > window mode is not used (CS[WIN] is 0), writing to WIN is not required to > make the new configuration take effect. > 8<---------------------------------------------------------------------- >=20 > > Support for 32-bit unlock command write words in enabled in > > imx7ulp_wdt_init now. >=20 > So.. after reading the IMX7ULP RM, which was not my intention, I found ou= t > that most of the WDOG_CS regiter bits are write-once bits. This means if = you > didn't set it within the bootloader you still in case "59.4.3.1". >=20 > So the imx7ulp_wdt_init() function just needs to check if the > WDOG_CS_UPDATE bit was set. If it is not the case, then you need to write= the > WDOG_CS register as currently done. If the bit is set, than you need know= that > the bootloader did the job for you and you can exit > imx7ulp_wdt_init() early. In both cases the unlock is not required. >=20 > Can you please check/test if this is working for you? >=20 > Regards, > Marco >=20 Hi Marco, Rom code has already configured the WDOG once, so we cannot use " Configuri= ng the Watchdog Once". Best Regards, Alice Guo