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From:   <Conor.Dooley@microchip.com>
To:     <heiko@sntech.de>, <tglx@linutronix.de>, <maz@kernel.org>,
        <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
        <palmer@dabbelt.com>, <paul.walmsley@sifive.com>,
        <aou@eecs.berkeley.edu>, <linux-riscv@lists.infradead.org>
CC:     <daniel.lezcano@linaro.org>, <anup@brainfault.org>,
        <Conor.Dooley@microchip.com>, <guoren@kernel.org>,
        <sagar.kadam@sifive.com>, <jrtc27@jrtc27.com>,
        <ajones@ventanamicro.com>, <linux-kernel@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <qemu-riscv@nongnu.org>,
        <robh@kernel.org>
Subject: Re: [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic:
 add legacy riscv compatible
Thread-Topic: [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic:
 add legacy riscv compatible
Thread-Index: AQHYtx72QjT8DbZ4AUeIZ7mMwDZq162+VAYAgAADEoA=
Date:   Wed, 24 Aug 2022 17:55:17 +0000
Message-ID: <95fe8df7-581e-f7ec-be1f-1c6e06cb30a4@microchip.com>
References: <20220823183319.3314940-1-mail@conchuod.ie>
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