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Date:   Wed, 24 Aug 2022 15:29:49 -0500
From:   Bjorn Helgaas <helgaas@kernel.org>
To:     Krishna chaitanya chundru <quic_krichai@quicinc.com>
Cc:     linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,
        linux-kernel@vger.kernel.org, mka@chromium.org,
        quic_vbadigan@quicinc.com, quic_hemantk@quicinc.com,
        quic_nitegupt@quicinc.com, quic_skananth@quicinc.com,
        quic_ramkri@quicinc.com, manivannan.sadhasivam@linaro.org,
        swboyd@chromium.org, dmitry.baryshkov@linaro.org
Subject: Re: [PATCH v5 0/3] PCI: Restrict pci transactions after pci suspend
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On Wed, Aug 03, 2022 at 04:58:51PM +0530, Krishna chaitanya chundru wrote:
> If the endpoint device state is D0 and irq's are not freed, then
> kernel try to mask interrupts in system suspend path by writing in to
> the vector table (for MSIX interrupts) and config space (for MSI's).

If clocks are being turned off while the PCI core is still accessing
the device, I think that means qcom suspend is not implemented
correctly.

> These transactions are initiated in the pm suspend after pcie clocks got
> disabled as part of platform driver pm  suspend call. Due to it, these
> transactions are resulting in un-clocked access and eventually to crashes.
> 
> So added a logic in qcom driver to restrict these unclocked access.
> And updated the logic to check the link state before masking
> or unmasking the interrupts.
> 
> And some devices are taking time to settle the link in L1ss, so added a
> retry logic in the suspend ops.
> 
> Krishna chaitanya chundru (3):
>   PCI: qcom: Add system PM support
>   PCI: qcom: Restrict pci transactions after pci suspend
>   PCI: qcom: Add retry logic for link to be stable in L1ss
> 
>  drivers/pci/controller/dwc/pcie-designware-host.c |  14 ++-
>  drivers/pci/controller/dwc/pcie-qcom.c            | 117 +++++++++++++++++++++-
>  2 files changed, 127 insertions(+), 4 deletions(-)
> 
> -- 
> 2.7.4
>