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Message-ID: <781356a88b502661ec23b3869679d80cf682017d.camel@mediatek.com>
Subject: Re: [PATCH] dt-bindings: arm: mediatek: mmsys: change compatible
 for MT8195
From:   Bo-Chen Chen <rex-bc.chen@mediatek.com>
To:     Matthias Brugger <matthias.bgg@gmail.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "krzysztof.kozlowski+dt@linaro.org" 
        <krzysztof.kozlowski+dt@linaro.org>
CC:     Jason-JH Lin =?UTF-8?Q?=28=E6=9E=97=E7=9D=BF=E7=A5=A5=29?= 
        <Jason-JH.Lin@mediatek.com>,
        Nancy Lin =?UTF-8?Q?=28=E6=9E=97=E6=AC=A3=E8=9E=A2=29?= 
        <Nancy.Lin@mediatek.com>,
        "CK Hu =?UTF-8?Q?=28=E8=83=A1=E4=BF=8A=E5=85=89=29?=" 
        <ck.hu@mediatek.com>,
        "chunkuang.hu@kernel.org" <chunkuang.hu@kernel.org>,
        "angelogioacchino.delregno@collabora.com" 
        <angelogioacchino.delregno@collabora.com>,
        "hsinyi@google.com" <hsinyi@google.com>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-mediatek@lists.infradead.org" 
        <linux-mediatek@lists.infradead.org>,
        Project_Global_Chrome_Upstream_Group 
        <Project_Global_Chrome_Upstream_Group@mediatek.com>
Date:   Thu, 25 Aug 2022 19:06:18 +0800
In-Reply-To: <f7ec45b8-ccd7-4776-0524-269e3188883d@gmail.com>
References: <20220825055658.12429-1-rex-bc.chen@mediatek.com>
         <3ff08ae9-a4b6-2b74-23cb-69ea1d7e1033@linaro.org>
         <d5a00dc88bed1680caa8af895a1140324b9d079e.camel@mediatek.com>
         <f7ec45b8-ccd7-4776-0524-269e3188883d@gmail.com>
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On Thu, 2022-08-25 at 18:55 +0800, Matthias Brugger wrote:
> 
> On 25/08/2022 08:59, Bo-Chen Chen wrote:
> > On Thu, 2022-08-25 at 14:11 +0800, Krzysztof Kozlowski wrote:
> > > On 25/08/2022 08:56, Bo-Chen Chen wrote:
> > > > From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com>
> > > > 
> > > > For previous MediaTek SoCs, such as MT8173, there are 2 display
> > > > HW
> > > > pipelines binding to 1 mmsys with the same power domain, the
> > > > same
> > > > clock driver and the same mediatek-drm driver.
> > > > 
> > > > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines
> > > > binding
> > > > to
> > > > 2 different power domains, different clock drivers and
> > > > different
> > > > mediatek-drm drivers.
> 
> drop clock driver example here.
> 

Hello Matthias,

Thanks for your review.
I am not sure what do you mean.
Could you explain more detailedly?

> > > 
> > > I don't see binding to different clock drivers and anyway that's
> > > not
> > > really an argument here. Please focus in description on hardware
> > > properties, IOW, are devices compatible or different. What is the
> > > incompatible difference between VDOSYS0 and 1?
> > > 
> > > Best regards,
> > > Krzysztof
> > 
> > Hello Krzysztof,
> > 
> > Thanks for yor review.
> > 
> >  From the functions perspective:
> > 
> > Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR,
> > AAL,
> > GAMMA, DITHER.
> > They are related to PQ (Picture Quality) functions and they makes
> > VDOSYS0 supports PQ function while they are not including in
> > VDOSYS1.
> > 
> > Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
> > component).
> > It makes VDOSYS1 supports the HDR function while it's not including
> > in
> > VDOSYS0.
> > 
> 
> Please include a description of this in the commit message.
> 

Yes, I have sent v2 and add these to commit meesage.

https://lore.kernel.org/all/20220825091448.14008-1-rex-bc.chen@mediatek.com/

BRs,
Bo-chen

> > About mediatek ETHDR, you can refer to this series:
> > 
> > 
https://lore.kernel.org/all/20220819061456.8042-2-nancy.lin@mediatek.com/
> > 
> > To summary:
> > Only VDOSYS0 can support PQ adjustment.
> > Only VDOSYS1 can support HDR adjustment.
> > 
> > Is this description ok for you?
> > If it is ok, I will put them into commit message in next version.
> > 
> > BRs,
> > Bo-Chen
> >