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From:   Conor Dooley <mail@conchuod.ie>
To:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Conor Dooley <conor.dooley@microchip.com>,
        Daire McNamara <daire.mcnamara@microchip.com>
Cc:     Sagar Kadam <sagar.kadam@sifive.com>,
        Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
        Atish Patra <atishp@atishpatra.org>,
        devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org
Subject: [PATCH 0/2] Add a PolarFire SoC l2 compatible
Date:   Thu, 25 Aug 2022 19:04:16 +0100
Message-Id: <20220825180417.1259360-1-mail@conchuod.ie>
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From: Conor Dooley <conor.dooley@microchip.com>

Whilst re-running checks before sending my dt-fixes PR today I noticed
that I had introduced another dtbs_check warning by applying one of the
patches in it.

PolarFire SoC has 4 cache interrupts, unlike the fu540 (which the dts
re-uses the compatible of currently) which only has 3. Add a new string
to the binding like should've been done in the first place...

The driver does not care which compatible it matches against, and just
uses as many interrupts as are in the dts so will happily work away
without any needed changes there.

@Palmer, you can take this directly as long as my fixes PR for rc3 is
merged if you like, since the application path for the binding is via
you anyway. I suppose I could take both too, but whatever works best
for you (:

Thanks,
Conor.

Conor Dooley (2):
  dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible
  riscv: dts: microchip: use an mpfs specific l2 compatible

 .../bindings/riscv/sifive-l2-cache.yaml       | 79 ++++++++++++-------
 arch/riscv/boot/dts/microchip/mpfs.dtsi       |  2 +-
 2 files changed, 50 insertions(+), 31 deletions(-)

-- 
2.37.1