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From:   <Conor.Dooley@microchip.com>
To:     <heinrich.schuchardt@canonical.com>, <Conor.Dooley@microchip.com>
CC:     <sagar.kadam@sifive.com>, <atishp@atishpatra.org>,
        <paul.walmsley@sifive.com>, <krzysztof.kozlowski+dt@linaro.org>,
        <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, <aou@eecs.berkeley.edu>,
        <Daire.McNamara@microchip.com>, <palmer@dabbelt.com>,
        <robh+dt@kernel.org>
Subject: Re: [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC
 compatible
Thread-Topic: [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC
 compatible
Thread-Index: AQHYuK1cgpDU3PrXM02UEZyzROk5r62/8euAgAAFkACAAA7cgIAAA+gA
Date:   Thu, 25 Aug 2022 20:03:54 +0000
Message-ID: <38981c6e-40cc-7468-b1ef-f4b3f341f3fd@microchip.com>
References: <20220825180417.1259360-1-mail@conchuod.ie>
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