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Date:   Thu, 25 Aug 2022 14:50:38 -0700
From:   Isaku Yamahata <isaku.yamahata@gmail.com>
To:     Binbin Wu <binbin.wu@linux.intel.com>
Cc:     isaku.yamahata@intel.com, kvm@vger.kernel.org,
        linux-kernel@vger.kernel.org, isaku.yamahata@gmail.com,
        Paolo Bonzini <pbonzini@redhat.com>, erdemaktas@google.com,
        Sean Christopherson <seanjc@google.com>,
        Sagi Shahar <sagis@google.com>
Subject: Re: [PATCH v8 013/103] KVM: TDX: Define TDX architectural definitions
Message-ID: <20220825215038.GD2538772@ls.amr.corp.intel.com>
References: <cover.1659854790.git.isaku.yamahata@intel.com>
 <f6bbcf4fb65a3de2ee7d4b2baa2965e24b0ede90.1659854790.git.isaku.yamahata@intel.com>
 <b19f28ac-07e0-2bd2-1b2e-abf7373b0960@linux.intel.com>
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On Thu, Aug 11, 2022 at 11:15:07AM +0800,
Binbin Wu <binbin.wu@linux.intel.com> wrote:

> > +/* @field is any of enum tdx_guest_other_state */
> > +#define TDVPS_STATE(field)		BUILD_TDX_FIELD(17, (field))
> > +#define TDVPS_STATE_NON_ARCH(field)	BUILD_TDX_FIELD_NON_ARCH(17, (field))
> > +
> > +/* Management class fields */
> > +enum tdx_guest_management {
> 
> More accurate to use tdx_vcpu_management?

Thanks for pointing it out.  I cleaned up it as follows for more consitency
and better match with the TDX module.

/* Class code for TD */
#define TD_CLASS_EXECUTION_CONTROLS     17ULL

/* Class code for TDVPS */
#define TDVPS_CLASS_VMCS                0ULL
#define TDVPS_CLASS_GUEST_GPR           16ULL
#define TDVPS_CLASS_OTHER_GUEST         17ULL
#define TDVPS_CLASS_MANAGEMENT          32ULL

enum tdx_tdcs_execution_control {
        TD_TDCS_EXEC_TSC_OFFSET = 10,
};

/* @field is any of enum tdx_tdcs_execution_control */
#define TDCS_EXEC(field)                BUILD_TDX_FIELD(TD_CLASS_EXECUTION_CONTROLS, (field))

/* @field is the VMCS field encoding */
#define TDVPS_VMCS(field)               BUILD_TDX_FIELD(TDVPS_CLASS_VMCS, (field))

enum tdx_vcpu_guest_other_state {
        TD_VCPU_STATE_DETAILS_NON_ARCH = 0x100,
};

union tdx_vcpu_state_details {
        struct {
                u64 vmxip       : 1;
                u64 reserved    : 63;
        };
        u64 full;
};

/* @field is any of enum tdx_guest_other_state */
#define TDVPS_STATE(field)              BUILD_TDX_FIELD(TDVPS_CLASS_OTHER_GUEST, (field))
#define TDVPS_STATE_NON_ARCH(field)     BUILD_TDX_FIELD_NON_ARCH(TDVPS_CLASS_OTHER_GUEST, (field))

/* Management class fields */
enum tdx_vcpu_guest_management {
        TD_VCPU_PEND_NMI = 11,
};

/* @field is any of enum tdx_vcpu_guest_management */
#define TDVPS_MANAGEMENT(field)         BUILD_TDX_FIELD(TDVPS_CLASS_MANAGEMENT, (field))

-- 
Isaku Yamahata <isaku.yamahata@gmail.com>