Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Fri, 26 Aug 2022 11:56:42 -0300
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     Lu Baolu <baolu.lu@linux.intel.com>
Cc:     Joerg Roedel <joro@8bytes.org>,
        Christoph Hellwig <hch@infradead.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Kevin Tian <kevin.tian@intel.com>,
        Ashok Raj <ashok.raj@intel.com>, Will Deacon <will@kernel.org>,
        Robin Murphy <robin.murphy@arm.com>,
        Jean-Philippe Brucker <jean-philippe@linaro.com>,
        Dave Jiang <dave.jiang@intel.com>,
        Fenghua Yu <fenghua.yu@intel.com>,
        Vinod Koul <vkoul@kernel.org>,
        Eric Auger <eric.auger@redhat.com>,
        Liu Yi L <yi.l.liu@intel.com>,
        Jacob jun Pan <jacob.jun.pan@intel.com>,
        Zhangfei Gao <zhangfei.gao@linaro.org>,
        Zhu Tony <tony.zhu@intel.com>, iommu@lists.linux.dev,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
        Jean-Philippe Brucker <jean-philippe@linaro.org>
Subject: Re: [PATCH v12 12/17] arm-smmu-v3/sva: Add SVA domain support
Message-ID: <YwjfKsvKyXLdCJ/Z@nvidia.com>
References: <20220826121141.50743-1-baolu.lu@linux.intel.com>
 <20220826121141.50743-13-baolu.lu@linux.intel.com>
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20220826121141.50743-13-baolu.lu@linux.intel.com>
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?RCu1vzO6I/1tA25bSqSAU3oElN65Y6iYD+bZYeI7/Y9JlzCst56fTq9KR9wI?=
 =?us-ascii?Q?N6xixsAKt3CaUYIq3MuMT5rEDLlo896FUiZxnwmh+2hA7f08goh++gkCC7//?=
 =?us-ascii?Q?hvdW32t8Q3CZpp2WuT3ITgYfAG6xiTruXPseGApf4rqZB4ScDjL7n9P2aGeX?=
 =?us-ascii?Q?deDcL1hCiyUkUi4rH2+BIfvVT96njYx7H/W/TV4iKp1SeJtbEOgfPEY71zK9?=
 =?us-ascii?Q?Teh1y6Xa+qBvaQE5sdYSllBJsoPTUQkDS0ZWV2nAt7aBFr/yAXawhDyFc8EV?=
 =?us-ascii?Q?SvF6a06466GT+0BS0YQF3fdEUyP5qc3MFguF+Z/mUCySx1/MjhIGiQqAme9J?=
 =?us-ascii?Q?vbzyoleaTavXTTZWdRudJEWB3qh2uHnPYxIrB7N6R7I3xCJff9P0pIxDlyAG?=
 =?us-ascii?Q?TSOy0FGP6YadsXwIRHwOkMnstQNoJarjRGbJgwGyCV7A/HybQfhr4GT/msjT?=
 =?us-ascii?Q?u47r5nUx99Z012lqMXam4zQyqTjzoqSK9yPktER/ofr6ghnjlPX6sMeuxWyf?=
 =?us-ascii?Q?He/TytkOuyJ34K8VKGnYmmRnH+oy6LyEJogIcbXuIfKk8pt2NnO6cq3ki/0L?=
 =?us-ascii?Q?OaOb86f+XMMwetLsNn7M0Ee0Rb7SkTzFs0HPrsYO7H+iuusgiI2ymtnHSwaD?=
 =?us-ascii?Q?btZIbH+XaInDCGdnfQn5CAV0VmwlgKG7tUpZAIvV40XpVT1J69EHxVLqCfuq?=
 =?us-ascii?Q?EakYprFQYs2TXoQzzLriXD8KbT03DU8HQ+H9No/Lya0cTx1Mp1nNgyLoJCps?=
 =?us-ascii?Q?cCfFU66uj+wcWd11ZzOD0RI7gIY+Ar5+qBguq2qBdjN13Tr4hyfZ/w/YuNmn?=
 =?us-ascii?Q?AnT1XVWMDJCSr5O5o/xm6HZwxeW3E/QCDWgbFf0dVDCHEszWZ6yvStciKTaD?=
 =?us-ascii?Q?zK9HC0/ssw4wkbAJcJqM39rnD+3VC4UviZmumMl8TXG9Mn+dp0V/9kxmArwg?=
 =?us-ascii?Q?pGY9Ga3n+xb+UeWNCKP3eR2jevxfJ/gPik3an40jX2ipii48Ws78vxHnDyQP?=
 =?us-ascii?Q?dKP0yfattjEOiCYQvw2g+k4TurAOKzqT60pdiMqsZBzZ8XkHHIWrBLQZQ0gb?=
 =?us-ascii?Q?KIw1gBdejuLpr0EdgJ2dglg9udkmWEyJMqqHyAZTyexMw8DIxHvHPtdPWjml?=
 =?us-ascii?Q?+f9zkYvzsKE+7FrlUYelL2bqNOHX6YVKWxamDEmeaIc9M4ItuJilBRmP7lS8?=
 =?us-ascii?Q?eWN0uFlQB4HEcw6pnPd3O6xslEhUTzeK07ES2w0EK7ncoy0IHzAXah4LXpbg?=
 =?us-ascii?Q?qWU9iGRYoS3HSYV2He3ia07ykOlxfVCS2Qsa6nRIHzNX4AYxI5ma+B9yANVX?=
 =?us-ascii?Q?BQugMFEn+FOnC3LaeDm3YU3tQJGxQE+aPwCFt1AhJqjNHLxobjPCAT3mVeiT?=
 =?us-ascii?Q?zr78IFhzsLrTmSlTJVaP5vtFLSdzqucBUzLNa8vSuJjjrrh9jc4ezu3GX/oV?=
 =?us-ascii?Q?JUoFVva90TwTtbVVmdHZ7915Dd8b9C+xUwE7muz3ZEaazu7b9ez7c58ENXR0?=
 =?us-ascii?Q?f217m8Z20EUjlTF5p8rJngsrAW6j6MxYGQQ+0cs/DNCdMTEMC8lGW5U8e2qV?=
 =?us-ascii?Q?WO79obEvvaTK2G117q+RZP8JEXCRmO1CK83P8q9x?=
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-Network-Message-Id: a153b5e1-1f7b-4acf-c2c5-08da87733087
X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB4192.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Aug 2022 14:56:43.3725
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: 0ECE7U0Ktcll9mpjCpZzbEIt8gi8La9co9dc0OQlvezCav2pFegBXs+J3M3Xg5He
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4138
X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
        DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,
        RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,
        T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Fri, Aug 26, 2022 at 08:11:36PM +0800, Lu Baolu wrote:

> +static const struct iommu_domain_ops arm_smmu_sva_domain_ops = {
> +	.set_dev_pasid		= arm_smmu_sva_set_dev_pasid,

Do we want to permit drivers to not allow a SVA domain to be set on a
RID?

It seems like a weird restriction to me

Jason