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[2620:137:e000::1:20]) by mx.google.com with ESMTP id c3-20020aa7df03000000b00447d567a77dsi2947779edy.207.2022.08.27.08.17.32; Sat, 27 Aug 2022 08:17:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=S9AhIjNx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233408AbiH0PNL (ORCPT + 99 others); Sat, 27 Aug 2022 11:13:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233384AbiH0PNI (ORCPT ); Sat, 27 Aug 2022 11:13:08 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C39929CBE for ; Sat, 27 Aug 2022 08:13:07 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 19E41B808BF for ; Sat, 27 Aug 2022 15:13:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D2CA1C433C1; Sat, 27 Aug 2022 15:13:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1661613184; bh=5SNvnZMs1SKkIb2edRqrtUf5+QVsBSTktjQt9Y2dpYg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=S9AhIjNxDtaN/V1OOjKPRv7HQs2ZNsKg3sxO81ZmnOlqWZ06/XWH48f1Kd3DjXFim H8fk8hF3H+XIKWSfqfVAEFTGdUxzaWMNsheuTyc2gj82eaJCvoMFAOTxsD8PPttwID h0dJBq7z+lCq8tGy1/33qbkzgI03jjD1M5ZIypK6v2fR40VQ+H/ibRJ+W/5eeGRUo8 CO87/fqX9WSajDBbB17YK71nVyFO4q8vZc3Zf6mLSzveGSNGG5UkAS4p8wPrRYxkge nWQUwnG4RwJxNr41Aa2R+l7GwEwG/62BNinSIov30fVzkylp6w4UgdZZn07nbBsLSP vsvji7eXxcXPg== Received: from [12.191.126.171] (helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oRxUc-006B4L-9R; Sat, 27 Aug 2022 16:13:02 +0100 Date: Sat, 27 Aug 2022 16:13:00 +0100 Message-ID: <87wnatra83.wl-maz@kernel.org> From: Marc Zyngier To: Puyou Lu Cc: Thomas Gleixner , Robert Richter , Catalin Marinas , linux-kernel@vger.kernel.org Subject: Re: [PATCH] irqchip/gic-v3: do runtime cpu cap check only when necessary In-Reply-To: <20220827051328.GA18042@lu-N56VJ> References: <20220827051328.GA18042@lu-N56VJ> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 12.191.126.171 X-SA-Exim-Rcpt-To: puyou.lu@gmail.com, tglx@linutronix.de, rrichter@cavium.com, catalin.marinas@arm.com, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 27 Aug 2022 06:19:27 +0100, Puyou Lu wrote: > > Now cpu cap check is done every exception happens on every arm64 platform, > but this check is necessary on just few of then, so we can drop this > check at compile time on others. This can decrease exception handle time > on most cases. > > Fixes: 6d4e11c5e2e8 ("irqchip/gicv3: Workaround for Cavium ThunderX erratum 23154") > Signed-off-by: Puyou Lu > --- > drivers/irqchip/irq-gic-v3.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index 262658fd5f9e..3f08c2ef1251 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -237,9 +237,11 @@ static void gic_redist_wait_for_rwp(void) > > static u64 __maybe_unused gic_read_iar(void) > { > +#ifdef CONFIG_CAVIUM_ERRATUM_23154 > if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) > return gic_read_iar_cavium_thunderx(); > else > +#endif > return gic_read_iar_common(); > } > #endif You realise that cpus_have_const_cap() results purely in a couple of branches once the caps have been finalised, right? Please provide data showing that it actually "can decrease exception handle time on most cases", because I'm pretty sure you cannot measure the difference in any meaningful way. M. -- Without deviation from the norm, progress is not possible.