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From:   "Datta, Shubhrajyoti" <shubhrajyoti.datta@amd.com>
To:     "quanyang.wang@windriver.com" <quanyang.wang@windriver.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Michal Simek <michal.simek@xilinx.com>
CC:     Michael Tretter <m.tretter@pengutronix.de>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH] clk: zynqmp: pll: rectify rate rounding in
 zynqmp_pll_round_rate
Thread-Topic: [PATCH] clk: zynqmp: pll: rectify rate rounding in
 zynqmp_pll_round_rate
Thread-Index: AQDcf5P6NtAgSeODCl3uhXFlQArgNa+/b3lw
Date:   Tue, 30 Aug 2022 06:18:55 +0000
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References: <20220826142030.213805-1-quanyang.wang@windriver.com>
In-Reply-To: <20220826142030.213805-1-quanyang.wang@windriver.com>
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[AMD Official Use Only - General]

Hi ,
Thanks for the patch.

> -----Original Message-----
> From: quanyang.wang@windriver.com <quanyang.wang@windriver.com>
> Sent: Friday, August 26, 2022 7:51 PM
> To: Michael Turquette <mturquette@baylibre.com>; Stephen Boyd
> <sboyd@kernel.org>; Michal Simek <michal.simek@xilinx.com>
> Cc: Michael Tretter <m.tretter@pengutronix.de>; Quanyang Wang
> <quanyang.wang@windriver.com>; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: [PATCH] clk: zynqmp: pll: rectify rate rounding in
> zynqmp_pll_round_rate
>=20
> CAUTION: This message has originated from an External Source. Please use
> proper judgment and caution when opening attachments, clicking links, or
> responding to this email.
>=20
>=20
> From: Quanyang Wang <quanyang.wang@windriver.com>
>=20
> The function zynqmp_pll_round_rate is used to find a most appropriate PLL
> frequency which the hardware can generate according to the desired
> frequency. For example, if the desired frequency is 297MHz, considering t=
he
> limited range from PS_PLL_VCO_MIN (1.5GHz) to PS_PLL_VCO_MAX (3.0GHz)
> of PLL, zynqmp_pll_round_rate should return 1.872GHz (297MHz * 5).
>=20
> There are two problems with the current code of zynqmp_pll_round_rate:
>=20
> 1) When the rate is below PS_PLL_VCO_MIN, it can't find a correct rate wh=
en
> the parameter "rate" is an integer multiple of *prate, in other words, if=
 "f" is
> zero, zynqmp_pll_round_rate won't return a valid frequency which is from
> PS_PLL_VCO_MIN to PS_PLL_VCO_MAX. For example, *prate is 33MHz and
> the rate is 660MHz, zynqmp_pll_round_rate will not boost up rate and just
> return 660MHz, and this will cause clk_calc_new_rates failure since
> zynqmp_pll_round_rate returns an invalid rate out of its boundaries.
>=20
> 2) Even if the rate is higher than PS_PLL_VCO_MIN, there is still a risk =
that
> zynqmp_pll_round_rate returns an invalid rate because the function
> DIV_ROUND_CLOSEST makes some loss in the fractional part. If the parent
> clock *prate is 33333333Hz and we want to set the PLL rate to 1.5GHz, thi=
s
> function will return 1499999985Hz by using the formula below:
>     value =3D *prate * DIV_ROUND_CLOSEST(rate, *prate)).
> This value is also invalid since it's slightly smaller than PS_PLL_VCO_MI=
N.
> because DIV_ROUND_CLOSEST makes some loss in the fractional part.
>=20
> Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>