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From:   Jerome Brunet <jbrunet@baylibre.com>
To:     Yu Tu <yu.tu@amlogic.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
        Neil Armstrong <narmstrong@baylibre.com>,
        Kevin Hilman <khilman@baylibre.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: Re: [PATCH V3 2/6] arm64: dts: meson: add S4 Soc PLL clock
 controller in DT
Date:   Tue, 30 Aug 2022 08:36:00 +0200
In-reply-to: <72631035-58a6-23b5-1f7e-f1643b120432@amlogic.com>
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On Tue 30 Aug 2022 at 14:05, Yu Tu <yu.tu@amlogic.com> wrote:

> On 2022/8/29 17:43, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>> On Mon 15 Aug 2022 at 14:17, Yu Tu <yu.tu@amlogic.com> wrote:
>>=20
>>> Hi Jerome=EF=BC=8C
>>>
>>> On 2022/8/10 21:32, Jerome Brunet wrote:
>>>> [ EXTERNAL EMAIL ]
>>>> On Fri 05 Aug 2022 at 17:39, Yu Tu <yu.tu@amlogic.com> wrote:
>>>>
>>>>> Hi Krzysztof,
>>>>>       Thank you for your reply.
>>>>>
>>>>> On 2022/8/5 17:16, Krzysztof Kozlowski wrote:
>>>>>> [ EXTERNAL EMAIL ]
>>>>>> On 05/08/2022 10:57, Yu Tu wrote:
>>>>>>> Added information about the S4 SOC PLL Clock controller in DT.
>>>>>>>
>>>>>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>>>>>> ---
>>>>>>>     arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 8 ++++++++
>>>>>>>     1 file changed, 8 insertions(+)
>>>>>>>
>>>>>>> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64=
/boot/dts/amlogic/meson-s4.dtsi
>>>>>>> index ff213618a598..a816b1f7694b 100644
>>>>>>> --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
>>>>>>> +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
>>>>>>> @@ -92,6 +92,14 @@ apb4: apb4@fe000000 {
>>>>>>>     			#size-cells =3D <2>;
>>>>>>>     			ranges =3D <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
>>>>>>>     +			clkc_pll: pll-clock-controller@8000 {
>>>>>> Node names should be generic - clock-controller.
>>>>>> https://devicetree-specification.readthedocs.io/en/latest/chapter2-d=
evicetree-basics.html#generic-names-recommendation
>>>>>>
>>>>> I will change to clkc_pll: clock-controller@8000, in next version.
>>>> Same comment applies to the binding doc.
>>> OKay.
>>>> Also it would be nice to split this in two series.
>>>> Bindings and drivers in one, arm64 dt in the other. These changes goes
>>>> in through different trees.
>>> At present, Bindings, DTS and drivers are three series. Do you mean to =
put
>>> Bindings and drivers together? If so, checkpatch.pl will report a warni=
ng.
>> Yes because patches are not in yet so there is a good reason to ignore
>> the warning. Warning will never show up on the actual tree if the
>> patches are correctly ordered.
>
> I think Binding, DTS and drivers use three series and you said two series
> is not a big problem. Three series are recommended for checkpatch.pl, I
> think it should be easy for that to separate and merge=E3=80=82

No - There is only 2 series. 1 for the bindings and clock drivers and
one for the DT once things are in

>
> I've sent it to V4. Please look at V4 and give some comments.
>

That's not how it works. You sent that before v3 review was done. There
are still comments that needed to be addressed

Given the time it takes to make that review I going to completly skip v4
and I'd like on the comment to addressed before you send another version


>>=20
>>>
>>>>
>>>>>> Best regards,
>>>>>> Krzysztof
>>>>>> .
>>>> .
>> .