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Message-ID: <879a6823-6651-93cf-8500-661bedb050af@codethink.co.uk>
Date:   Tue, 30 Aug 2022 11:44:43 +0100
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Subject: Re: [PATCH v2 6/9] riscv: dts: microchip: icicle: update pci address
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To:     Conor Dooley <conor.dooley@microchip.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Daire McNamara <daire.mcnamara@microchip.com>,
        Shravan Chippa <shravan.chippa@microchip.com>
Cc:     Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Cyril Jean <Cyril.Jean@microchip.com>,
        Lewis Hanly <lewis.hanly@microchip.com>,
        Vattipalli Praveen <praveen.kumar@microchip.com>,
        Wolfgang Grandegger <wg@aries-embedded.de>,
        Hugh Breslin <hugh.breslin@microchip.com>,
        devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org
References: <20220830101803.1456180-1-conor.dooley@microchip.com>
 <20220830101803.1456180-7-conor.dooley@microchip.com>
From:   Ben Dooks <ben.dooks@codethink.co.uk>
Organization: Codethink Limited.
In-Reply-To: <20220830101803.1456180-7-conor.dooley@microchip.com>
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On 30/08/2022 11:18, Conor Dooley wrote:
> For the v2022.09 reference design the PCI root port's data region has
> been moved to FIC1 from FIC0. This is a shorter path, allowing for
> higher clock rates and improved through-put. As a result, the address at
> which the PCIe's data region appears to the core complex has changed.
> The config region's address is unchanged.

Did this also fix the 32bit address apperture issue which plagued
getting pcie graphics cards sorted.


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

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