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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CH2PR12MB4264.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 64b97130-7346-4ff2-f882-08da8a717e9d X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Aug 2022 10:22:08.6409 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pc1xScnzgSeuHd3TNkatyBNgvApQL4oeaYljS35Zn+vBMsam8lJkPLuXmr+/Sb8+OHhUmuZQFG+o723XLaseAw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1811 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Michael, > -----Original Message----- > From: Michael Walle > Sent: Tuesday, August 30, 2022 12:40 PM > To: Potthuri, Sai Krishna > Cc: Tudor Ambarus ; Pratyush Yadav > ; Miquel Raynal ; > Richard Weinberger ; Vignesh Raghavendra > ; Rob Herring ; Krzysztof Kozlowski > ; devicetree@vger.kernel.org; linux- > mtd@lists.infradead.org; linux-kernel@vger.kernel.org; > saikrishna12468@gmail.com; git (AMD-Xilinx) > Subject: Re: [PATCH 2/2] mtd: spi-nor: Add support for flash reset >=20 > Hi, >=20 > Am 2022-08-30 08:32, schrieb Potthuri, Sai Krishna: >=20 > >> > + if (ret) > >> > + return ret; > >> > + > >> > + /* > >> > + * Experimental Minimum Chip select high to Reset delay value > >> > + * based on the flash device spec. > >> > + */ > >> > >> Which flash device spec? > > I referred some of the qspi, ospi flash vendors datasheets like > > Micron, Macronix, ISSI, gigadevice, spansion. >=20 > Please mention here that you've looked at datasheets of different vendors= . > And maybe instead of doing three comments, just one and then the reset > sequence. Ok, I will update in v2. >=20 > >> > >> > + usleep_range(1, 5); > >> > + gpiod_set_value(reset, 0); > >> > >> Mh, is your logic inverted here? If I read the code correctly, you > >> should use a value of 1 to take the device into reset. The device > >> tree should then have a flag "active low", which will > > Reset Sequence which I implemented here is high(1)->low(0)->high(1). > > By doing this sequence (active low), flash device is getting reset, > > this sequence is tested using Octal SPI flash device. >=20 > How does the device tree property for your look like? > Has it the GPIO_ACTIVE_LOW flag set? Sorry, I misunderstand your initial ask, This logic is developed by keeping the GPIO_ACTIVE_HIGH flag set in the device-tree. Agree this will violate t= he flash reset sequence (active low reset). I will update the sequence in v2 to match with the "active low" flag in the device tree. Regards Sai Krishna >=20 > -michael