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Date:   Tue, 30 Aug 2022 13:25:40 -0500
From:   Rob Herring <robh@kernel.org>
To:     Nava kishore Manne <nava.kishore.manne@amd.com>
Cc:     git@amd.com, krzysztof.kozlowski+dt@linaro.org,
        michal.simek@xilinx.com, mdf@kernel.org, hao.wu@intel.com,
        yilun.xu@intel.com, trix@redhat.com, p.zabel@pengutronix.de,
        gregkh@linuxfoundation.org, ronak.jain@xilinx.com,
        rajan.vaja@xilinx.com, abhyuday.godhasara@xilinx.com,
        piyush.mehta@xilinx.com, lakshmi.sai.krishna.potthuri@xilinx.com,
        harsha.harsha@xilinx.com, linus.walleij@linaro.org,
        nava.manne@xilinx.com, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-fpga@vger.kernel.org
Subject: Re: [PATCH 2/4] bindings: fpga: Add binding doc for the zynqmp afi
 config driver
Message-ID: <20220830182540.GA1797396-robh@kernel.org>
References: <20220824035542.706433-1-nava.kishore.manne@amd.com>
 <20220824035542.706433-3-nava.kishore.manne@amd.com>
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On Wed, Aug 24, 2022 at 09:25:40AM +0530, Nava kishore Manne wrote:
> Xilinx Zynq US+ MPSoC platform connect the PS to the programmable
> logic(PL) through the AXI port. This AXI port helps to establish
> the data path between the PS and PL. In-order to establish the proper
> communication data path between PS and PL the AXI port data path should
> be configured with the proper Bus-width values.
> 
> This patch adds the binding document for the zynqmp afi config driver
> to handle the AXI port bus-width configurations and PS-PL resets.
> 
> Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> ---
>  .../bindings/fpga/xlnx,zynqmp-afi-fpga.yaml   | 100 ++++++++++++++++++
>  1 file changed, 100 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
> 
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
> new file mode 100644
> index 000000000000..faae4951e991
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
> @@ -0,0 +1,100 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-afi-fpga.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx ZynqMP AFI interface Manager.
> +
> +maintainers:
> +  - Nava kishore Manne <nava.kishore.manne@amd.com>
> +
> +description: The Zynq UltraScale+ MPSoC Processing System core provides access
> +  from PL masters to PS internal peripherals, and memory through AXI FIFO
> +  interface(AFI)
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - xlnx,zynqmp-afi-fpga
> +
> +  resets:
> +    description:
> +      A list of phandles for resets listed in reset-names.
> +
> +  reset-names:
> +    items:
> +      - const: pl0-rst
> +      - const: pl1-rst
> +      - const: pl2-rst
> +      - const: pl3-rst

Not all that useful of names given it is just indices. Minimally, '-rst' 
is redundant and I don't know what 'pl' means.

> +
> +patternProperties:
> +  "^xlnx,afifm[0-6]-rd-bus-width$":
> +    description: bus width used to configure the afifm-rd interface.

...width in bits...

> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [ 32, 64, 128 ]
> +
> +  "^xlnx,afifm[0-6]-wr-bus-width$":

Can combine these 2:

"^xlnx,afifm[0-6]-(wr|rd)-bus-width$"

> +    description: bus width used to configure the afifm-wr interface.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [ 32, 64, 128 ]
> +
> +  "^xlnx,afifs-ss[0-2]-bus-width$":
> +    description: bus width used to configure the afifs interface.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [ 32, 64, 128 ]
> +
> +required:
> +  - compatible
> +  - xlnx,afifm0-rd-bus-width
> +  - xlnx,afifm1-rd-bus-width
> +  - xlnx,afifm2-rd-bus-width
> +  - xlnx,afifm3-rd-bus-width
> +  - xlnx,afifm4-rd-bus-width
> +  - xlnx,afifm5-rd-bus-width
> +  - xlnx,afifm6-rd-bus-width
> +  - xlnx,afifm0-wr-bus-width
> +  - xlnx,afifm1-wr-bus-width
> +  - xlnx,afifm2-wr-bus-width
> +  - xlnx,afifm3-wr-bus-width
> +  - xlnx,afifm4-wr-bus-width
> +  - xlnx,afifm5-wr-bus-width
> +  - xlnx,afifm6-wr-bus-width
> +  - xlnx,afifs-ss0-bus-width
> +  - xlnx,afifs-ss1-bus-width
> +  - xlnx,afifs-ss2-bus-width
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
> +    zynqmp-afi {
> +      compatible = "xlnx,zynqmp-afi-fpga";
> +      xlnx,afifm0-rd-bus-width = <32>;
> +      xlnx,afifm1-rd-bus-width = <32>;
> +      xlnx,afifm2-rd-bus-width = <64>;
> +      xlnx,afifm3-rd-bus-width = <128>;
> +      xlnx,afifm4-rd-bus-width = <32>;
> +      xlnx,afifm5-rd-bus-width = <64>;
> +      xlnx,afifm6-rd-bus-width = <128>;
> +      xlnx,afifm0-wr-bus-width = <32>;
> +      xlnx,afifm1-wr-bus-width = <32>;
> +      xlnx,afifm2-wr-bus-width = <64>;
> +      xlnx,afifm3-wr-bus-width = <128>;
> +      xlnx,afifm4-wr-bus-width = <32>;
> +      xlnx,afifm5-wr-bus-width = <64>;
> +      xlnx,afifm6-wr-bus-width = <128>;
> +      xlnx,afifs-ss0-bus-width = <64>;
> +      xlnx,afifs-ss1-bus-width = <64>;
> +      xlnx,afifs-ss2-bus-width = <64>;
> +      resets = <&zynqmp_reset ZYNQMP_RESET_PS_PL0>,
> +               <&zynqmp_reset ZYNQMP_RESET_PS_PL1>,
> +               <&zynqmp_reset ZYNQMP_RESET_PS_PL2>,
> +               <&zynqmp_reset ZYNQMP_RESET_PS_PL3>;
> +      reset-names = "pl0-rst", "pl1-rst", "pl2-rst", "pl3-rst";

Should devices on this bus be child devices or do they fit on some other 
bus?

> +    };
> +
> +...
> -- 
> 2.25.1
> 
>