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 <fdec1b72-27f3-96e6-5e19-d54ded4aea68@microchip.com> <cefcf96f-5bcc-d134-fbe5-d1169313b6f3@codethink.co.uk>
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From:   Zong Li <zongbox@gmail.com>
Date:   Wed, 31 Aug 2022 13:22:41 +0800
Message-ID: <CA+ZOyajWRUFppg26O1XHfRuJHWB3jk-=-i=FBV9XYgHgshuwQA@mail.gmail.com>
Subject: Re: [PATCH] soc: sifive: ccache: reduce printing on init
To:     Ben Dooks <ben.dooks@codethink.co.uk>
Cc:     Conor.Dooley@microchip.com, ben.dooks@sifive.com,
        zong.li@sifive.com, palmer@dabbelt.com, paul.walmsley@sifive.com,
        aou@eecs.berkeley.edu, greentime.hu@sifive.com,
        linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
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Ben Dooks <ben.dooks@codethink.co.uk> =E6=96=BC 2022=E5=B9=B48=E6=9C=8831=
=E6=97=A5 =E9=80=B1=E4=B8=89 =E5=87=8C=E6=99=A81:04=E5=AF=AB=E9=81=93=EF=BC=
=9A
>
> On 30/08/2022 17:30, Conor.Dooley@microchip.com wrote:
> > On 30/08/2022 09:26, Ben Dooks wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know=
 the content is safe
> >>
> >> The driver prints out 6 lines on startup, which can easily be redcued
> >> to two lines without losing any information.
> >>
> >> Note, to make the types work better, uint64_t has been replaced with
> >> ULL to make the unsigned long long match the format in the print
> >> statement.
> >>
> >> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
> >> ---
> >>   drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
> >>   1 file changed, 11 insertions(+), 14 deletions(-)
> >>
> >> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/s=
ifive_ccache.c
> >> index 46ce33db7d30..65a10a6ee211 100644
> >> --- a/drivers/soc/sifive/sifive_ccache.c
> >> +++ b/drivers/soc/sifive/sifive_ccache.c
> >> @@ -76,20 +76,17 @@ static void setup_sifive_debug(void)
> >>
> >>   static void ccache_config_read(void)
> >>   {
> >> -       u32 regval, val;
> >> -
> >> -       regval =3D readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> >> -       val =3D regval & 0xFF;
> >> -       pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
> >> -       val =3D (regval & 0xFF00) >> 8;
> >> -       pr_info("CCACHE: No. of ways per bank: %d\n", val);
> >> -       val =3D (regval & 0xFF0000) >> 16;
> >> -       pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
> >> -       val =3D (regval & 0xFF000000) >> 24;
> >> -       pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 <=
< val);
> >> -
> >> -       regval =3D readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> >> -       pr_info("CCACHE: Index of the largest way enabled: %d\n", regv=
al);
> >> +       u32 cfg;
> >> +
> >> +       cfg =3D readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> >> +
> >> +       pr_info("CCACHE: %u banks, %u ways, sets/bank=3D%llu, bytes/bl=
ock=3D%llu\n",
> >> +               (cfg & 0xff), (cfg >> 8) & 0xff,
> >> +               1ULL << ((cfg >> 16) & 0xff),
> >
> > This is just BIT_ULL((cfg >> 16) & 0xff), no?
> > Would be nice too if these were defined, so you'd have something
> > like BIT_ULL((cfg >> SETS_PER_BANK_SHIFT) & 0xff)
> >
> > I do like the cleanup of the uint64_t & cutting down on the prints
> > though :) Again, it'd be nice if you and Zong could collaborate on
> > a combined v2.
>
> I think even BIT_UL() would do here, if someone is going to make a
> cache bigger than 2GiB we'll probably be quite old by then, so v2
> might have the last two values down as %lu.
>

Hi Ben,
Thanks for your suggestion, If you don't mind, I will take this into
my V2 patchset.

> > Thanks,
> > Conor.
> >
> >> +               1ULL << ((cfg >> 24) & 0xff));
> >> +
> >> +       cfg =3D readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> >> +       pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg)=
;
> >>   }
> >>
> >>   static const struct of_device_id sifive_ccache_ids[] =3D {
> >> --
> >> 2.35.1
> >>
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
>
> --
> Ben Dooks                               http://www.codethink.co.uk/
> Senior Engineer                         Codethink - Providing Genius
>
> https://www.codethink.co.uk/privacy.html
>
>
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