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Date:   Wed, 31 Aug 2022 12:42:48 +0300 (EEST)
From:   =?ISO-8859-15?Q?Ilpo_J=E4rvinen?= <ilpo.jarvinen@linux.intel.com>
To:     Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
cc:     Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Jiri Slaby <jirislaby@kernel.org>, andy.shevchenko@gmail.com,
        u.kleine-koenig@pengutronix.de, johan@kernel.org,
        wander@redhat.com, etremblay@distech-controls.com,
        macro@orcam.me.uk, geert+renesas@glider.be, jk@ozlabs.org,
        phil.edworthy@renesas.com, Lukas Wunner <lukas@wunner.de>,
        LKML <linux-kernel@vger.kernel.org>,
        linux-serial <linux-serial@vger.kernel.org>,
        UNGLinuxDriver@microchip.com
Subject: Re: [PATCH v1 tty-next 1/2] 8250: microchip: pci1xxxx: Add driver
 for the quad-uart function in the  multi-function endpoint of pci1xxxx
 device.
In-Reply-To: <20220830180054.1998296-2-kumaravel.thiagarajan@microchip.com>
Message-ID: <bea049b-69d-a097-ddeb-737cdd485e@linux.intel.com>
References: <20220830180054.1998296-1-kumaravel.thiagarajan@microchip.com> <20220830180054.1998296-2-kumaravel.thiagarajan@microchip.com>
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Precedence: bulk

On Tue, 30 Aug 2022, Kumaravel Thiagarajan wrote:

> pci1xxxx is a PCIe switch with a multi-function endpoint on one of its
> downstream ports. Quad-uart is one of the functions in the
> multi-function endpoint. This driver loads for the quad-uart and
> enumerates single or multiple instances of uart based on the PCIe
> subsystem device ID.
> 
> Signed-off-by: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
> ---

> +static int mchp_pci1xxxx_rs485_config(struct uart_port *port,
> +				      struct ktermios *termios,
> +				      struct serial_rs485 *rs485)
> +{
> +	u8 data = 0;
> +
> +	memset(rs485->padding, 0, sizeof(rs485->padding));
> +	rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
> +
> +	if (rs485->flags & SER_RS485_ENABLED) {
> +		data = ADCL_CFG_EN | ADCL_CFG_PIN_SEL;
> +		if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) {
> +			data |= ADCL_CFG_POL_SEL;
> +			rs485->flags |=  SER_RS485_RTS_AFTER_SEND;
> +		}
> +	}
> +
> +	rs485->delay_rts_after_send = 0;
> +	rs485->delay_rts_before_send = 0;
> +	writeb(data, (port->membase + ADCL_CFG_REG));
> +	port->rs485 = *rs485;

Most of this will be handled for by the core so don't duplicate it in
the driver.

These days, you also need to provide rs485_supported.

> +	return 0;
> +}
> +
> +static void mchp_pci1xxxx_set_termios(struct uart_port *port,
> +				      struct ktermios *termios,
> +				      struct ktermios *old)
> +{
> +	const unsigned int standard_baud_list[] = {50, 75, 110, 134, 150, 300,
> +						600, 1200, 1800, 2000, 2400, 3600,
> +						4800, 7200, 9600, 19200, 38400, 57600,
> +						115200, 125000, 136400, 150000, 166700,
> +						187500, 214300, 250000, 300000, 375000,
> +						500000, 750000, 1000000, 1500000};
> +	unsigned int baud = tty_termios_baud_rate(termios);
> +	unsigned int baud_clock;
> +	unsigned int quot;
> +	unsigned int frac;
> +	unsigned int i;
> +
> +	baud = tty_termios_baud_rate(termios);

Either this or the one at the declaration is redundant.

> +	serial8250_do_set_termios(port, termios, NULL);
> +
> +	if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
> +		writel((port->custom_divisor & 0x3FFFFFFF),
> +		       (port->membase + CLK_DIVISOR_REG));
> +	} else {
> +		for (i = 0; i < ARRAY_SIZE(standard_baud_list); i++) {
> +			if (baud == standard_baud_list[i])
> +				return;

Did you mean to break here instead?

> +		}
> +		tty_termios_encode_baud_rate(termios, baud, baud);
> +
> +		baud = uart_get_baud_rate(port, termios, old,
> +					  50, 1500000);
> +		baud_clock = readb(port->membase + CLK_SEL_REG);
> +
> +		if ((baud_clock & CLK_SEL_MASK) == CLK_SEL_500MHZ) {
> +			quot = 500000000 / (16 * baud);
> +			writel(quot, (port->membase + CLK_DIVISOR_REG));
> +		} else if ((baud_clock & CLK_SEL_MASK) == CLK_SEL_166MHZ) {
> +			quot = (166667 * 1000) / (16 * baud);
> +			writel(quot, (port->membase + CLK_DIVISOR_REG));
> +		} else {
> +			quot = ((1000000000) / (baud * UART_BIT_SAMPLE_CNT));
> +			frac = (((1000000000 - (quot * baud *
> +				UART_BIT_SAMPLE_CNT)) / UART_BIT_SAMPLE_CNT)
> +				* 255) / baud;
> +			writel(frac | (quot << 8),
> +			       (port->membase + CLK_DIVISOR_REG));
> +		}

Please check ->[gs]et_divisor() out.


-- 
 i.