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Date:   Wed, 31 Aug 2022 12:12:22 +0100
From:   Jonathan Cameron <Jonathan.Cameron@huawei.com>
To:     Robert Richter <rrichter@amd.com>
CC:     Alison Schofield <alison.schofield@intel.com>,
        Vishal Verma <vishal.l.verma@intel.com>,
        Ira Weiny <ira.weiny@intel.com>,
        Ben Widawsky <bwidawsk@kernel.org>,
        Dan Williams <dan.j.williams@intel.com>,
        <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        "Rafael J. Wysocki" <rafael@kernel.org>,
        Len Brown <lenb@kernel.org>
Subject: Re: [PATCH 08/15] cxl/acpi: Check RCH's CXL DVSEC capabilities
Message-ID: <20220831121222.00000977@huawei.com>
In-Reply-To: <20220831115224.00003afd@huawei.com>
References: <20220831081603.3415-1-rrichter@amd.com>
        <20220831081603.3415-9-rrichter@amd.com>
        <20220831115224.00003afd@huawei.com>
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On Wed, 31 Aug 2022 11:52:24 +0100
Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote:

> On Wed, 31 Aug 2022 10:15:56 +0200
> Robert Richter <rrichter@amd.com> wrote:
> 
> > An RCH has an RCiEP connected to it with CXL DVSEC capabilities
> > present and the CXL PCIe DVSEC included. Check this.
> > 
> > Signed-off-by: Robert Richter <rrichter@amd.com>  
> One comment inline. This looks good to me.
> 
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> > ---
> >  drivers/cxl/acpi.c | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> > 
> > diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> > index ffdf439adb87..f9cdf23a91a8 100644
> > --- a/drivers/cxl/acpi.c
> > +++ b/drivers/cxl/acpi.c
> > @@ -322,6 +322,8 @@ struct pci_host_bridge *cxl_find_next_rch(struct pci_host_bridge *host)
> >  {
> >  	struct pci_bus *bus = host ? host->bus : NULL;
> >  	struct acpi_device *adev;
> > +	struct pci_dev *pdev;
> > +	bool is_restricted_host;
> >  
> >  	while ((bus = pci_find_next_bus(bus)) != NULL) {
> >  		host = bus ? to_pci_host_bridge(bus->bridge) : NULL;
> > @@ -343,6 +345,20 @@ struct pci_host_bridge *cxl_find_next_rch(struct pci_host_bridge *host)
> >  		dev_dbg(&host->dev, "PCI ACPI host found: %s\n",
> >  			acpi_dev_name(adev));
> >  
> > +		/* Check CXL DVSEC of dev 0 func 0 */  
> 
> So assumption here is that the hostbridge has a one or more RCiEPs.
> The spec (r3.0 9.11.4) allows for the EP to appear behind a root port
> - that case always felt odd to me, so I'm fine with not supporting it until
> we see a user.
> 
> > +		pdev = pci_get_slot(bus, PCI_DEVFN(0, 0));
> > +		is_restricted_host = pdev
> > +			&& (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
> > +			&& pci_find_dvsec_capability(pdev,
> > +						PCI_DVSEC_VENDOR_ID_CXL,
> > +						CXL_DVSEC_PCIE_DEVICE);

Thinking a bit more on this.  I'm not sure this is sufficient.
Nothing in CXL 2.0 or later prevents true RCiEP devices (there are a
few references in CXL 3.0 e.g. 9.12.1 has RCDs or CXL RCiEPs - so just
detecting that there is one on the host bridge might not be sufficient
to distinguish this from a non RCH / RCB.

> > +		pci_dev_put(pdev);
> > +
> > +		if (!is_restricted_host)
> > +			continue;
> > +
> > +		dev_dbg(&host->dev, "CXL restricted host found\n");
> > +
> >  		return host;
> >  	}
> >  
> > @@ -354,6 +370,7 @@ static int __init cxl_restricted_host_probe(struct platform_device *pdev)
> >  	struct pci_host_bridge *host = NULL;
> >  
> >  	while ((host = cxl_find_next_rch(host)) != NULL) {
> > +		dev_info(&host->dev, "host supports CXL\n");
> >  	}
> >  
> >  	return 0;  
>