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From:   Conor Dooley <mail@conchuod.ie>
To:     Paul Walmsley <paul.walmsley@sifive.com>,
        Rob Herring <robh+dt@kernel.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Daire McNamara <daire.mcnamara@microchip.com>,
        Conor Dooley <mail@conchuod.ie>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc:     Conor Dooley <conor.dooley@microchip.com>,
        linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
        Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
        Sagar Kadam <sagar.kadam@sifive.com>,
        Atish Patra <atishp@atishpatra.org>,
        devicetree@vger.kernel.org, ben.dooks@sifive.com,
        zong.li@sifive.com
Subject: Re: [PATCH 0/2] Add a PolarFire SoC l2 compatible
Date:   Wed, 31 Aug 2022 17:13:50 +0100
Message-Id: <166196217701.591052.12924322910945691679.b4-ty@microchip.com>
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From: Conor Dooley <conor.dooley@microchip.com>

On Thu, 25 Aug 2022 19:04:16 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Whilst re-running checks before sending my dt-fixes PR today I noticed
> that I had introduced another dtbs_check warning by applying one of the
> patches in it.
> 
> PolarFire SoC has 4 cache interrupts, unlike the fu540 (which the dts
> re-uses the compatible of currently) which only has 3. Add a new string
> to the binding like should've been done in the first place...
> 
> [...]

@Palmer, I have applied these to my dt-fixes, branch as the commit they
fix is there too. As I mentioned on IRC, patches for this dt-binding are
usually merged via the riscv tree so I have taken the liberty of bundling
it with the dts change. You may get this in a PR friday morning, but more
likely early next week.

Conor.


[1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible
      https://git.kernel.org/conor/c/17e4732d1d8a
[2/2] riscv: dts: microchip: use an mpfs specific l2 compatible
      https://git.kernel.org/conor/c/0dec364ffeb6

Thanks,
Conor.