Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
MIME-Version: 1.0
From:   Tim Harvey <tharvey@gateworks.com>
Date:   Wed, 31 Aug 2022 13:18:46 -0700
Message-ID: <CAJ+vNU1F3sYuSX9HEpVEPb-NzFEaKnuc_5mznTHOLFmCkCu_Lg@mail.gmail.com>
Subject: cn9130-crb PCI support
To:     kostap@marvell.com
Cc:     Miquel Raynal <miquel.raynal@bootlin.com>,
        Kishon Vijay Abraham I <kishon@ti.com>,
        Vinod Koul <vkoul@kernel.org>,
        Rob Herring <robh+dt@kernel.org>, Andrew Lunn <andrew@lunn.ch>,
        gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com,
        vladimir.vid@sartura.hr, luka.kovacic@sartura.hr,
        linux-phy@lists.infradead.org,
        Device Tree Mailing List <devicetree@vger.kernel.org>,
        open list <linux-kernel@vger.kernel.org>,
        Linux ARM Mailing List <linux-arm-kernel@lists.infradead.org>,
        mw@semihalf.com, jaz@semihalf.com, nadavh@marvell.com,
        stefanc@marvell.com, bpeled@marvell.com
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

Konstantin,

In commit 5c0ee54723f3 ("arm64: dts: add support for Marvell
cn9130-crb platform") which added support for the cn9130-crb where are
the PCI RESET# and CLKREQ# pins configured and specified?

As PCIE_PERST# is connected to CP_MPP[52] on the board I expected to
either see something like:
cp0_pci_pins: cp0-pci-pins-0 {
     marvell,pins = "mpp52";
     marvell,function = "pci";
};

or:
&cp0_pcie0 {
    gpios-reset = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
};

I don't see any support in the PCIe driver (marvell,armada8k-pcie,
snps,dw-pcie) that support gpios-reset.

I'm working on support for another cn9130 board and am unclear how to
configure the pinctrl for PERST# as well as CLKREQ3. Any pointers
would be greatly appreciated.

Best Regards,

Tim