Received: by 2002:a05:6358:45e:b0:b5:b6eb:e1f9 with SMTP id 30csp975069rwe; Wed, 31 Aug 2022 14:41:22 -0700 (PDT) X-Google-Smtp-Source: AA6agR6WgsPNrOFasXFYpPnTTSqV18sYSaRzxs7oNdit1qKuVF7jN9Dv/azQ/lnQDn5waL2l3kG8 X-Received: by 2002:a17:902:e552:b0:16d:c98c:5954 with SMTP id n18-20020a170902e55200b0016dc98c5954mr28027577plf.111.1661982081947; Wed, 31 Aug 2022 14:41:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1661982081; cv=none; d=google.com; s=arc-20160816; b=mqpTbUBUZfYbYQ/jgvy+/r93muznJQR9R9KouSVmdu87tSqUNV+zCb5XuECVDTgvrM JncZad6j9iN+R7wQ33LQ8EXKOBBGpHKcyUMSJUI2/OV1L08IBVKENRDtNJ8izhgTS4CO Qu2AIv3/ZOBeiQfjnS4LepT9SJz1o0r2pw0IZrlv2JYTYT99mxL1mpViYtUgR+nXv561 ozeMvJ628EnUUrn++n5Jg6KesxcK+f65dDygd3CNFBOIfAdUUvcHQhN1EjSJxeiknm8j 4UOf83kmvpTCoC0q12/XG5U4vZsXuxDCnrM6y645Ejoe1ZJMoyyHegbVFihWrQ5Ob34Q GNQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=F77ZSMjukIX1htEAuPVZavphrGy3kQNsKQQbF8+npDM=; b=JVmcTjbvTPCIXYKGYH6Ij93juKEOeHqpIphjZGmLuMkCpYN+BULpm8qZ/RxoD8m+Wm l/W6KoFQL6NJNmGOSfribM6uYIPRoWHA63H5KxLJeGqTrV/84wOmGfyoEcQ+eO70tWvN 6eWdCbFHjxFvHr6arSZ2zQHTkco5QNul+cWBvtOP73MHK8gIbMneLp9lFuju8V7uDOge hF7WdDGnznS4r7moikoS3mQU/4KmedfMnhU0uPHgPzmEFZHj+im4OnWKsPd9MvNOlyTG /78LGyaI/TyS+3v/Q5ScvqiqD6RfJ4F7A6wSp3fNtz+iUO2ZPOSWvzTThERuUIqUKyGL +Nmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=NXj8J5KN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f21-20020a056a00239500b005108171fe28si16422116pfc.162.2022.08.31.14.41.01; Wed, 31 Aug 2022 14:41:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=NXj8J5KN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230444AbiHaUv3 (ORCPT + 99 others); Wed, 31 Aug 2022 16:51:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229631AbiHaUv1 (ORCPT ); Wed, 31 Aug 2022 16:51:27 -0400 Received: from mail-qv1-xf32.google.com (mail-qv1-xf32.google.com [IPv6:2607:f8b0:4864:20::f32]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 04182F14F0; Wed, 31 Aug 2022 13:51:24 -0700 (PDT) Received: by mail-qv1-xf32.google.com with SMTP id q8so12014044qvr.9; Wed, 31 Aug 2022 13:51:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=F77ZSMjukIX1htEAuPVZavphrGy3kQNsKQQbF8+npDM=; b=NXj8J5KNtB1xYx+f13xUMw7aGumHqDF3nK9EZZnacnmQhiz6vPl5kHqVXZbOydNbYJ XMAQDyHyt6vKaRQeH+yV6z+K+eIC7id6NAB/7COEIkM1BTDOC9EjwwaNiuvW+wdAjY0l dKpV1Tl5ChwADCOAyYBF9fvDKZQF0KTSWr91lW0h+BojNDMFuXYRFVTeBdL9UGbewrXn hRxxKPBljR5zzZWuuGawiJRUH1S2we8mSEOHwmYMgPDM/v/+fm2mmMLGs6zOqwVgQ/qv xktlK9j0x2zTy1I4ImVbXZU4U04FZovhERko4AFaBRjHK1rtDEyDSRbIJYBx/G3PIaGg ut/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=F77ZSMjukIX1htEAuPVZavphrGy3kQNsKQQbF8+npDM=; b=dIsZfId2qhHTBcQMxOr6qyVweYqS/fAAzvCyJTvfUQX2yXwLZUVVd0pBMN0i/nytJv MNdlsyUe+k3XmEhL3j/cTMvk+P+GTIdHHtLC1CZgCMQf19uC0YV4yWIzf+r90LHx9RlG 3BlZ2L9cRdd2E9KrjclzHkg37Q22DwHRU+lKeS6n8ugGnTv1ao+9+SXjp/mm9YuSgJtJ 1ql4V7l/YQxl4EDVYMZjK11/b9YfGg9uWCpTalyt55k+XspHJJ3xWaeKPEYQqB8x6vha Iz5YBHtJn3Hxe3o9nmuZaI/daDAR5czLgv92CnhhI+R6VJkggttJILiAmlZdBGa+DiYK 7gdQ== X-Gm-Message-State: ACgBeo1YZ0e9ASEh3DYafztgJiznc5WLaZEKOz3dJ7tcHRybKYji48fW 8NvwDNf+l/NqtrjqZDpEpbCGsxooIfZhD2eSWno= X-Received: by 2002:a05:6214:27ca:b0:499:95f:6379 with SMTP id ge10-20020a05621427ca00b00499095f6379mr12248607qvb.82.1661979083135; Wed, 31 Aug 2022 13:51:23 -0700 (PDT) MIME-Version: 1.0 References: <20220831055811.1936613-1-s.hauer@pengutronix.de> <20220831055811.1936613-2-s.hauer@pengutronix.de> In-Reply-To: <20220831055811.1936613-2-s.hauer@pengutronix.de> From: Andy Shevchenko Date: Wed, 31 Aug 2022 23:50:47 +0300 Message-ID: Subject: Re: [PATCH v2 1/2] gpio: Add gpio latch driver To: Sascha Hauer Cc: "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Geert Uytterhoeven , Linus Walleij , Bartosz Golaszewski , Sascha Hauer Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 31, 2022 at 9:02 AM Sascha Hauer wrote: > > This driver implements a GPIO multiplexer based on latches connected to > other GPIOs. A set of data GPIOs is connected to the data input of > multiple latches. The clock input of each latch is driven by another > set of GPIOs. With two 8-bit latches 10 GPIOs can be multiplexed into > 16 GPIOs. GPOs might be a better term as in fact the multiplexed pins > are output only. I'm still unsure it shouldn't be a part of the (not yet in upstream) driver that I have mentioned before. But let's leave this apart right now. ... > +#include > +#include > +#include Why? It seems you misplaced it instead of mod_devicetable.h. > +#include > +#include > +#include Keep above sorted? ... > + struct mutex mutex; > + spinlock_t spinlock; Checkpatch usually complains if locks are not commented. Looking at the below code, why it's not an (anonymous) union? ... > + if (val) > + priv->shadow[latch] |= BIT(offset % priv->n_pins); > + else > + priv->shadow[latch] &= ~BIT(offset % priv->n_pins); I believe shadow should be defined as unsigned long * and hence normal bit operations can be applied. For example here is assign_bit(). ... > + priv->shadow = devm_kcalloc(&pdev->dev, priv->n_ports, sizeof(*priv->shadow), > + GFP_KERNEL); bitmap_zalloc() > + if (!priv->shadow) > + return -ENOMEM; ... > + priv->gc.parent = &pdev->dev; > + priv->gc.of_node = pdev->dev.of_node; Redundant as repeating parent above. ... > +static const struct of_device_id gpio_latch_ids[] = { > + { > + .compatible = "gpio-latch", > + }, { > + /* sentinel */ > + } You may compress this to the 2 LoCs. > +}; -- With Best Regards, Andy Shevchenko