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Date:   Thu, 1 Sep 2022 14:20:13 +0200
From:   Jesper Nilsson <Jesper.Nilsson@axis.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
CC:     "dj76.yang@samsung.com" <dj76.yang@samsung.com>,
        Jesper Nilsson <Jesper.Nilsson@axis.com>,
        Lars Persson <Lars.Persson@axis.com>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "krzk+dt@kernel.org" <krzk+dt@kernel.org>,
        "lee.jones@linaro.org" <lee.jones@linaro.org>,
        "javierm@redhat.com" <javierm@redhat.com>,
        "bjorn.andersson@linaro.org" <bjorn.andersson@linaro.org>,
        linux-arm-kernel <linux-arm-kernel@axis.com>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Moon-Ki Jun <moonki.jun@samsung.com>,
        Sang Min Kim <hypmean.kim@samsung.com>,
        Wangseok Lee <wangseok.lee@samsung.com>
Subject: Re: [PATCH 4/4] mfd: Samsung: Add Samsung sysmgr driver
Message-ID: <20220901122013.GU22198@axis.com>
References: <CGME20220713045746epcms1p302c6643d12ed505d24298e1edb5889ec@epcms1p3>
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Hi,


Thanks for your comments Krzysztof and sorry for being late in replying, I'll
try to fill in the blanks for some of the issues below.


The ARTPEC-8 is derived from a Samsung design, but built to order for Axis, so
long term responsibility will fall to Axis (me and Lars primarily).

The ARTPEC-6 and ARTPEC-7 were built by an other vendor and are quite different
not to mention that they are 32-bit ARMs, compared to ARM 64-bit for the ARTPEC-8.


The driver in this patchset is derived from the drivers/mfd/altera-sysmgr.c and
solves the same problem, in where the SoC system controller IP is a collection
of registers that controls quite a lot of different peripheral functions (from
PCIe and Ethernet to PWM) and is reachable only through SMC calls. I think the
naming of the software was set as samsung-sysmgr since it is not Axis design at
all, but (to my knowledge) only existing in ARTPEC-8 as yet. I can't recall why
the mfd driver route was selected, but it could be that the earlier
implementation was more complex and used both smc and direct mmio writes.

The users of this system manager would initially be the ARTPEC-8 DWC EQoS and
ARTPEC-8 DWC PCIe drivers sent in other patch-sets.


I believe a possible alternative to solve the system manager problem is to open
code the SMC calls directly from the drivers in question, quite a lot of
drivers seem to do this, notably a specific altera driver
(drivers/edac/altera_edac.c) even though it also has a reference to the above
mentioned altera-sysmgr regmap... :-)

Does that seem reasonable?

Thanks for your patience and excuses for the top-posting.

/Jesper

On Wed, Jul 13, 2022 at 09:27:52AM +0200, Krzysztof Kozlowski wrote:
> On 13/07/2022 06:57, Dongjin Yang wrote:
[...]

> Best regards,
> Krzysztof

/^JN - Jesper Nilsson
-- 
               Jesper Nilsson -- jesper.nilsson@axis.com