Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Message-ID: <e513fa856dc5c7b85a45057293f6e6549777a04e.camel@mediatek.com>
Subject: Re: [PATCH v17 06/10] drm/mediatek: dp: Add multiple calibration
 data formats support
From:   CK Hu <ck.hu@mediatek.com>
To:     Bo-Chen Chen <rex-bc.chen@mediatek.com>, <chunkuang.hu@kernel.org>,
        <p.zabel@pengutronix.de>, <daniel@ffwll.ch>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <mripard@kernel.org>,
        <tzimmermann@suse.de>, <matthias.bgg@gmail.com>, <deller@gmx.de>,
        <airlied@linux.ie>
CC:     <msp@baylibre.com>, <granquet@baylibre.com>,
        <jitao.shi@mediatek.com>, <wenst@chromium.org>,
        <angelogioacchino.delregno@collabora.com>,
        <liangxu.xu@mediatek.com>, <dri-devel@lists.freedesktop.org>,
        <linux-mediatek@lists.infradead.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-fbdev@vger.kernel.org>,
        <Project_Global_Chrome_Upstream_Group@mediatek.com>
Date:   Fri, 2 Sep 2022 15:38:51 +0800
In-Reply-To: <20220901044149.16782-7-rex-bc.chen@mediatek.com>
References: <20220901044149.16782-1-rex-bc.chen@mediatek.com>
         <20220901044149.16782-7-rex-bc.chen@mediatek.com>
Content-Type: text/plain; charset="UTF-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Precedence: bulk

Hi, Bo-Chen:

On Thu, 2022-09-01 at 12:41 +0800, Bo-Chen Chen wrote:
> The calibration data formats of eDP and DP are different. We add
> "const struct mtk_dp_efuse_fmt *efuse_fmt" to the device data to
> define them.

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> 
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dp.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c
> b/drivers/gpu/drm/mediatek/mtk_dp.c
> index 971bd744cdb2..136e13150281 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dp.c
> @@ -113,8 +113,10 @@ struct mtk_dp {
>  struct mtk_dp_data {
>  	int bridge_type;
>  	unsigned int smc_cmd;
> +	const struct mtk_dp_efuse_fmt *efuse_fmt;
>  };
> -static const struct mtk_dp_efuse_fmt
> mtk_dp_efuse_data[MTK_DP_CAL_MAX] = {
> +
> +static const struct mtk_dp_efuse_fmt
> mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = {
>  	[MTK_DP_CAL_GLB_BIAS_TRIM] = {
>  		.idx = 3,
>  		.shift = 27,
> @@ -811,7 +813,7 @@ static void mtk_dp_get_calibration_data(struct
> mtk_dp *mtk_dp)
>  	}
>  
>  	for (i = 0; i < MTK_DP_CAL_MAX; i++) {
> -		fmt = &mtk_dp_efuse_data[i];
> +		fmt = &mtk_dp->data->efuse_fmt[i];
>  		cal_data[i] = (buf[fmt->idx] >> fmt->shift) & fmt-
> >mask;
>  
>  		if (cal_data[i] < fmt->min_val || cal_data[i] > fmt-
> >max_val) {
> @@ -827,7 +829,7 @@ static void mtk_dp_get_calibration_data(struct
> mtk_dp *mtk_dp)
>  use_default_val:
>  	dev_warn(mtk_dp->dev, "Use default calibration data\n");
>  	for (i = 0; i < MTK_DP_CAL_MAX; i++)
> -		cal_data[i] = mtk_dp_efuse_data[i].default_val;
> +		cal_data[i] = mtk_dp->data->efuse_fmt[i].default_val;
>  }
>  
>  static void mtk_dp_set_calibration_data(struct mtk_dp *mtk_dp)
> @@ -1983,6 +1985,7 @@ static SIMPLE_DEV_PM_OPS(mtk_dp_pm_ops,
> mtk_dp_suspend, mtk_dp_resume);
>  static const struct mtk_dp_data mt8195_edp_data = {
>  	.bridge_type = DRM_MODE_CONNECTOR_eDP,
>  	.smc_cmd = MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE,
> +	.efuse_fmt = mt8195_edp_efuse_fmt,
>  };
>  
>  static const struct of_device_id mtk_dp_of_match[] = {