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[31.30.173.67]) by smtp.gmail.com with ESMTPSA id ay19-20020a05600c1e1300b003a50924f1c0sm1700998wmb.18.2022.09.02.02.49.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Sep 2022 02:49:40 -0700 (PDT) Date: Fri, 2 Sep 2022 11:49:39 +0200 From: Andrew Jones To: Heiko Stuebner Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, conor.dooley@microchip.com, guoren@kernel.org, apatel@ventanamicro.com, atishp@rivosinc.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing Message-ID: <20220902094939.wvzovl6ytujtjbtm@kamzik> References: <20220901222744.2210215-1-heiko@sntech.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220901222744.2210215-1-heiko@sntech.de> X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Heiko, Please use a cover-letter for a patch series. They allow the series to be threaded better and people can reply to the cover-letter with series-wide comments. For example, I'd like to reply to a cover-letter now with For the series Reviewed-by: Andrew Jones but now it looks like I need to go back and reply to each patch separately. Thanks, drew On Fri, Sep 02, 2022 at 12:27:41AM +0200, Heiko Stuebner wrote: > This can also do without the ifdef and use IS_ENABLED instead and > for better readability, getting rid of that switch also seems > waranted. > > Signed-off-by: Heiko Stuebner > --- > arch/riscv/kernel/cpufeature.c | 13 +++++-------- > 1 file changed, 5 insertions(+), 8 deletions(-) > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 553d755483ed..764ea220161f 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void) > #ifdef CONFIG_RISCV_ALTERNATIVE > static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage) > { > -#ifdef CONFIG_RISCV_ISA_SVPBMT > - switch (stage) { > - case RISCV_ALTERNATIVES_EARLY_BOOT: > + if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT)) > return false; > - default: > - return riscv_isa_extension_available(NULL, SVPBMT); > - } > -#endif > > - return false; > + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) > + return false; > + > + return riscv_isa_extension_available(NULL, SVPBMT); > } > > static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage) > -- > 2.35.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv