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Date:   Fri, 2 Sep 2022 14:36:50 -0500
From:   Rob Herring <robh@kernel.org>
To:     Ben Dooks <ben.dooks@sifive.com>
Cc:     robh+dt@kernel.org, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org, conor.dooley@microchip.com,
        krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org,
        palmer@dabbelt.com, paul.walmsley@sifive.com,
        greentime.hu@sifive.com, aou@eecs.berkeley.edu
Subject: Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for
 l3 cache
Message-ID: <20220902193650.GA285986-robh@kernel.org>
References: <20220829062202.3287-1-zong.li@sifive.com>
 <20220830125133.1698781-1-ben.dooks@sifive.com>
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On Tue, 30 Aug 2022 13:51:33 +0100, Ben Dooks wrote:
> With newer cores such as the p550, the SiFive composable cache can be
> a level 3 cache. Update the cache level to be one of 2 or 3.
> 
> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
> ---
>  Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>